Chapter 9: DMA Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
9-17
Bit(s)
Field
R/W
Default
Description
29
GCCI
R/O
0
DMA Global Chain Mode Completion Interrupt
0: No Chain Mode completion interrupt in any DMA channel
1: Chain Mode completion interrupt in some DMA channels
28
GCBI
R/O
0
DMA Global C790 Bus Error Interrupt
0: No C790 bus error interrupt in any DMA channel
1: C790 bus error interrupt in some DMA channels
27
GGBI
R/O
0
DMA Global G-Bus Error Interrupt
0: No G-Bus error interrupt in any DMA channel
1: G-Bus error interrupt in some DMA channels
26:24
–
R/O
0
Reserved
23
GINTE
R/W
0
DMA Global Interrupt Enable
0: Disable All DMAC Interrupts.
1: Enable All DMAC Interrupts.
22:1
–
R/O
0
Reserved
0
FRP
R/W
0
Fixed/Round-robin Priority
0: Fixed
1: Round-robin
9.2.8
C790 Bus Error Address Register (CBEADDR)
Table 9-10 lists the fields of the C790 Bus Error Address Register.
63
32
0
32
31
0
CBEA[31:0]
32
Table 9-10 C790 Bus Error Address Register Field Descriptions
Bit(s)
Field
R/W
Default
Description
63:32
–
R/O
0
Reserved
31:0
CBEA
R/O
0
C790 Bus Error Address
When the DMAC is the master on the C790 bus and
encounters a bus error, the first bus error address is recorded
in this register. Further bus error addresses are ignored until
the C790 bus error interrupt (CBI) is cleared.
Содержание TMPR7901
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Страница 14: ...Handling Precautions ...
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