Toshiba TMPR7901, Руководство пользователя

Страница: 303 / 309

Chapter 16: Clocks
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
16-6
Table 16-4 Example Frequency Relationship
CpuClk
RefClk
2 3 4
SysClk gbusClk
133 MHz 266*
1
400*
2
533*
2
133 MHz 66 MHz
100 MHz 200 300*
2
400*
2
100 MHz 50 MHz
66 MHz 133 200 266
*1
66 MHz 33 MHz
50 MHz 100 150 200 50 MHz 25 MHz
*
1: Premium products only.
*2: Future product. Not guaranteed at this time.
16.4 Peripheral Module Clock
This section describes the clock requirements of the individual peripheral modules.
16.4.1 MAC Clock
Each 10/100 Ethernet module in the TX7901 is composed of a Tx clock domain and an Rx
clock domain. The Rx clock is reconstructed from the received data stream running at 10
MHz or 100 MHz. The reconstruction is done by an external 802.3 Physical Layer device.
The 2.5 / 10 MHz Rx clock is used for 10Base Ethernet configuration while the 25 MHz Rx
clock is used for 100Base Ethernet configuration.
The Tx clock is generated from an external oscillator. The external oscillator will generate a
reference clock to a PHY device. The PHY then constructs a very accurate 2.5 MHz / 10
MHz / 25 MHz TX clock which drives the TX7901 MAC module.
The FIFO structure inside the MAC module synchronizes data transfer between the MAC
clock and G-Bus Clock domain.
16.4.2 UART Clock
The UART module has a Transmit and a Receive clock domain. The Receive clock is an
input signal from the UART Receive channel. The Transmit clock is generated by the Baud
Rate Generator logic in the UART module. The Baud Rate Generation logic is a digital
frequency divider and is a sub-module of the UART.
The digital frequency divider takes two steps to generate a Transmit Clock. First, the
G-Bus Clock is divided down by a pre-scaler to generate the 8 MHz Clock. Then the 8 MHz
clock is divided down to the designated frequency. The Transmit and Receive frequencies’
range is between 50 Hz and 256 KHz. Both pre-scaler and Baud Rate dividers are
programmable. See Table 14-13 and Table 14-14 for more specific information.
The UART uses FIFO structures to synchronize between Transmit / Receive Logic and the
G-Bus.