Toshiba TMPR7901, Руководство пользователя

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Chapter 10: Programmable Timer/Contents
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
10-21
10.5.4 Examples of Timer/Counter Timing
These examples illustrate the different modes of operation of the various timers. (Refer to
Section 10.1 at the beginning of the chapter for details.)
10.5.4.1 Interval Timer Mode Interrupt Timing
Figure 10-7 illustrates a case in which Timer Compare Value A (TCVA) is “3”, and the timer
input clock is the 50 MHz internal G-Bus Clock. The Timer Interval Interrupt Status Bit (TIIS)
of the Interrupt Status Register TMTISR is set at the rising edge of the G-Bus Clock Input
Clock gbsBusClk when a match has been detected. The interrupt signal TMINTREQ* is
asserted synchronously with the internal system clock and the counter is simultaneously
cleared to “0” (assuming in this example that bit TZCE of the Interval Timer Mode Register
TMITMR, is set).
Figure 10-7 Interval Timing Example Using Internal Clock
The above figure illustrates a case in which Timer Compare Value A (TCVA) is “3”, and the
counter is triggered by the external clock input. The Timer’s Interval Timer Interrupt Status
bit TIIS of the Interrupt Status Register TMTISR is set at the rising edge of the External Input
Clock when a match has been detected and TMINTREQ* is asserted Low. Simultaneously,
the counter is cleared (assuming in this example that bit TZCE of the Interval Timer Mode
Register TMITMR is set).
Figure 10-8 Interval Timing Example Using External Input Clock
0 1 2 3 0 1 2 3
TMCLK
External
Input Clock
TMTCR.TCE
Count Value
Interrupt
Request Signal
TMTISR.TIIS
TMITMR.TIIE = 0
TMITMR.TIIE = 1
0 1 2 3 0 1 2 3
TMCLK
Timer Input
Clock
TMTCR.TCE
Count Value
Interrupt
Request Signal
TMTISR.TIIS
TMITMR.TIIE = 0
TMITMR.TIIE = 1