Toshiba TMPR7901, Руководство пользователя

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Chapter 6: SDRAM Memory Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
6-9
All of the following registers are 128 bits wide and are aligned to 16 Byte boundaries. In
order to facilitate Bi-Endian programming, it is strongly recommended to use lq/sq to access
these registers.
6.5.1 Parameters register
127 32
0
96
31 30 29 28 26 25 24 23 21 20 18 17 16 15 2 1 0
0
A
2
P
R
R
T
W
R
T
P
2
A
I
A
2
R
W
I
C
A
S
0
D
S
L
2 1 3 2 3 3 2 14 2
This register contains parameters that are used for each of the physical memory devices.
All memory devices share the same timing parameters (bits[29:16]) in the Device Region 0
Parameters Register.
DIMM 0 Parameters Register (0x1E00_0000) R/W
Field Bit(s) Description
Timing
Symbol
DSL 1:0
Device Select (01)
00 : 16 Mb SDRAM
01 : 64/128 Mb SDRAM
10 : 256 Mb SDRAM
11 : Reserved
–
– 15:2 Reserved –
CAS 17:16
CAS Latency (11)
These bits specify the timing for the first read data after
SDRAM samples a column address.
00, 01: Reserved
10 : 2 clock cycles
11 : 3 clock cycles
tCAS
A2RWI 20:18
Active to Read/Write Interval (011)
Specifies the earliest timing for a READ/WRITE command
after an ACTIVE command.
000, 001 : Reserved
010 : 2 clock cycles
011 : 3 clock cycles
100 - 111 : Reserved
tRCD
P2AI 23:21
Precharge to active interval (011)
These bits specify the earliest timing for a new command
after a PRECHARGE command.
000, 001 : Reserved
010 : 2 clock cycles
011 : 3 clock cycles
100 - 111 : Reserved
tRP
WRT 25:24
Write recovery time (10)
These bits specify the earliest timing for a PRECHARGE
command after the last data were written to the SDRAM.
01 : 1 clock cycle
10 : 2 clock cycles
00, 11 : Reserved
tWR