Toshiba TMPR7901, Руководство пользователя

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Chapter 6: SDRAM Memory Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
6-1
6. SDRAM Memory Controller
6.1 Overview
This SDRAM Controller is used to connect the C790 (128-bit MIPS CPU) to SDRAM. The
SDRAM devices that can be connected are 64 Mb, 128 Mb, or 256 Mb with a 4-bank
architecture. If 8M x 8 x 4 SDRAM chips are used, the TX7901 can support 1 GB memory
with 4 physical memory banks.
6.2 Features
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Directly connected to a 128-bit C790 sysbus operating up to 133 MHz
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Supports PC100/133 DIMM
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Supports 4-bank interleaving for 64/128/256 Mbit SDRAMs, or 2-bank
interleaving for 16 Mbit
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ECC, single-bit error correction, double-bit error detection
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Maximum access rate of 133 MHz
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Supports aligned (8 quad-word) burst transfers
6.3 Address Space Decoding
The SDRAM Controller has a fully programmable address map. It uses a two-stage
decoding process where major device regions are decoded first, and then the individual
devices are sub-decoded. Addresses for regions in 256 MB units are compared by exact
matching, and individual device addresses are compared by size comparison. One device
(DIMM) therefore cannot span across 256 MB boundaries.
6.4 Two-Stage Decoding Process
Physical space is divided into 16 regions. Each region can have 256 MBytes of address
space. Memory space decoding starts with the sysAddr address being compared with the
values in the four LOW and HIGH Registers. Device0, device1, device2, and device3
correspond to sdrCSB[0], sdrCSB[1], sdrCSB[2], sdrCSB[3.]
Address decoding is performed as follows:
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sysAddr[31:28] are compared against region field [31:28] in the LOW Decoder