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Programming and Parameters
PowerFlex 700S Phase II AC Drive User Manual -
Publication 20D-UM006G-EN-P – July 2008
267
Heidn Encdr PPR
Set this value equal to the Heidenhain encoder PPR (e.g., 2048). This value is automatically
set when bit 1 “NotEnDat” of parameter 266 [Heidn Encdr Type] is set to “0” (False).
Note: This parameter was added for firmware version 2.03. Changed the minimum value from
“10” to “1” for firmware version 4.001.
Units:
Default:
Min/Max:
PPR
2048
1/100000
RW 32-bit
Integer
268 Resolver0
Cnfg
Configures options for the resolver option card port 0.
•
Setting bit 0 “Cable Tune” enables the cable tuning test, resetting the bit to zero disables the test. Refer to the section on Resolver Cable Tuning Tests in
publication PFLEX-RM003, Reference Manual - PowerFlex 700S Drives with Phase II Control for more information.
•
Bit 1 “Tune Param” has been disabled.
•
Bits 2 “Resolution 0” and 3 “Resolution 1” select the resolver resolution (see
Table 268A: Resolution Settings
). This determines the number of significant bits
that are calculated in the value of
[FB Opt0 Posit]. It does not affect the number of counts created per resolver revolution (see
and Least Significant Bits Used
). Also, the resolution sets a limit on the maximum tracking speed (see
Table 268C: Resolution and Resolver Tracking Speed
).
•
Setting bit 4 “Energize” energizes the resolver, resetting the bit to zero de-energizes the resolver.
•
Bit 5 “Resolver Dir” determines counting direction. If clear, direction is forward or up. If set, the direction is reverse or down.
•
Bit 9 “Edge Time” configures the method of sampling used by the Velocity Position Loop (VPL). Setting the bit chooses "Edge to Edge" sampling, while resetting
the bit to zero chooses "Simple Difference" sampling. "Simple Difference" sampling calculates speed by examining the difference between pulse counts over a
fixed sample time. "Edge to Edge" sampling adjusts the sample time to synchronize with the position count updates from the daughter card - improving the
accuracy of the speed calculation.
•
Bits 10 “SmplRate bt0” through 12 “SmplRate bt2” configure the Finite Impulse Response (FIR) Filter (see
Table 268D: FIR Filter Settings
). This setting reduces
the effect of noisy feedback on the system. Refer to the Speed/Position Feedback section of the PowerFlex® 700S with Phase II Control Reference Manual,
publication PFLEX-RM003 for details.
Note: Bit 11 “SmplRate bt0” is set to 0 = False by default for firmware version 1.11 and bit 11 “SmplRate1” is set to 1 = True by default for firmware version 2.03.
No.
Name
Description
Values
Linkab
le
R
ead-Wr
ite
Da
ta
T
ype
Options
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
SmplRate b
t2
SmplRate b
t1
SmplRate b
t0
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Reso
lv
er
Dir
Ener
giz
e
Reso
lut
ion 1
Reso
lut
ion 0
Rese
rv
ed
Cab
le T
une
Default
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True
Table 268D: FIR Filter Settings
Bit 12 11 10 Taps
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
127
Table 268A: Resolution Settings
Table 268B: Resolution and Least Significant Bits Used
Table 268C: Resolution and Resolver Tracking Speed
Bit 3
2
Resolution
0
0
10 bit resolution
0
1
12 bit resolution (default setting)
1
0
14 bit resolution
1
1
16 bit resolution
Resolution LSB Not Used
Parameter 250 Increments by
16 bit
All bits used
1
14 bit
2 LSB not used 4
12 bit
4 LSB not used 8
10 bit
6 LSB not used 64
Resolution Maximum
Carrier Freq.
Tracking Speed
for X1 Resolver
Tracking Speed
for X2 Resolver
Tracking Speed
for X5 Resolver
10 bit
34 kHz
55 K-rpm
27.5 K-rpm
11 K-rpm
12 bit
24kHz
13.8 K-rpm
6.9 K-rpm
2.76 K-rpm
14 bit
14kHz
3480 rpm
1740 rpm
696 rpm
16 bit
10 kHz
900 rpm
450 rpm
180 rpm
Содержание PowerFlex 700S
Страница 1: ...USER MANUAL Firmware Versions 1 xxx 4 002 PowerFlex 700S High Performance AC Drive Phase II Control ...
Страница 58: ...2 8 Start Up PowerFlex 700S Phase II AC Drive User Manual Publication 20D UM006G EN P July 2008 Notes ...
Страница 147: ...Programming and Parameters 3 89 PowerFlex 700S Phase II AC Drive User Manual Publication 20D UM006G EN P July 2008 ...
Страница 278: ...D 8 HIM Overview PowerFlex 700S Phase II AC Drive User Manual Publication 20D UM006G EN P July 2008 Notes ...
Страница 316: ...Index 6 PowerFlex 700S Phase II AC Drive User Manual Publication 20D UM006G EN P July 2008 ...
Страница 317: ......