Mindray Z6, Руководство по обслуживанию

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Hardware Principle 4-13
No Controlling signal Description Remarks
2 SUS_S3_N CPU module output effectively represents that CPU
system has been in the standby status, when 5VSTB
which is controlled by power management FPGA is in the
charging status.
3 SUS_S4_N CPU module output effectively represents that CPU
system has been in the dormancy status.
4 PWR_OK_N The output of power supply module is transmitted to the
CPU module by power management FPGA, which
represents the +12V output of power supply module has
been powered on.
5 CPU_PWR_BTN_N Power management FPGA is transmitted to CPU, which
notifies CPU power on or power off.
6
PWR_12V_EN
The output of power management FPGA is transmitted
to the power supply module, which is used to control
other power of the DC-DC power board except 5VSTB
and 3V3STB to be power-on..
7
PWR_5VSTB_EN
The output of power management FPGA notifies power
to provide 5V standby power.
8
PWR_12V_OK_N
Power status signal; indicate 12V power has been
provided steadily.
9
PWR_5VSTB_OK_N
Power status signal; indicate 5VSTB power has been
provided steadily.

When battery and AC supply, the power supply module always maintains the 3V3STB output,
and supports power management FPGA of the power module to be standby status.

No matter the system is on when AC supply, Power management FPGA will always control
DC-DC power board to output 5VSTB via PWR_5VSTB_EN_N However, when powered by
battery, power management FPGA could control DC-DC power board to output 5VSTB though
PWR_5VSTB_EN_N if only users turn on the system via power button of the control panel.

The detailed flow of power-on is shown as follows: