Keysight Technologies Infiniium MSOV 084A, Руководство по обслуживанию

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Theory of Operation
7
Infiniium V-Series Oscilloscopes Service Guide 153
The main FPGA can be used to control peripherals and fan speed, configure and
communicate with other FPGAs, and pass sampled data to the PC for
reconstruction of the measured waveform on the oscilloscope display. In addition,
the FPGA generates PCI interrupts for all oscilloscope-related special events such
as a front-end overload or a stopped cooling fan.
The main FPGA uses three identical buses to communicate with three different
downstream FPGAs. The buses are 8-bit parallel buses with miscellaneous control
signals. One bus is used to control the trigger functions in the backplane board
and one bus connects to each of the two acquisition boards. A separate bus for
each FPGA minimizes timing problems and reflections. The FPGAs on the
acquisition assemblies are used to control the oscilloscope functions on each of
those assemblies. On power-up, after the PC software recognizes the two
acquisition assemblies, it loads the trigger FPGA and the acquisition FPGAs using
these buses. When programming is complete, the PC communicates with the
downstream FPGA over the same buses.
The main FPGA provides access to the memory controllers over a separate bus to
each acquisition board. The acquired data is retrieved from the acquisition boards
over these buses.
Timebase system
The oscilloscope timebase system generates and distributes all of the clock
signals that control or are synchronized to waveform acquisition. The following
figure shows the timebase system including its circuitry.