Intel® Server Board SE7520BD2 Technical Product Specification
Product Overview
Revision 1.3
Intel Confidential
23
GPO48/GNT4# Output
A4
Core
3.3V
FRB
Timer
Halt
2.9.1.10
Enhanced Power Management
The ICH5-R’s power management functions include enhanced clock control, local and global
monitoring support for 14 individual devices, and various low-power (suspend) states (e.g.,
Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management circuit
permits software-independent entrance to low-power states. The ICH5-R contains full support
for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0b.
2.9.1.11
System Management Bus (SMBus 2.0)
The ICH5-R contains an SMBus Host interface that allows the processor to communicate with
SMBus slaves. This interface is compatible with most I
2
C devices. Special I
2
C commands are
implemented. The ICH5-R’s SMBus host controller provides a mechanism for the processor to
initiate communications with SMBus peripherals (slaves). Also, the ICH5-R supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports eight
command protocols of the SMBus interface (see System Management Bus (SMBus)
Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read
Byte/Word, Process Call, Block Read/Write, and Host Notify.
2.9.2 PXH
The PXH provides the data interface between the MCH and two PCI-X bus segments over a
high-speed PCI-Express x8 link. Each of the two PCI segments in the PXH is individually
controlled to operate in either PCI or PCI-X mode.
The PXH is configured to support the following interfaces:
•
PCI-X 1.0 bus
o
Two hot-plug capable PCI-X slots and LSI* 1030C U320 SCSI controller on 100MHz
3.3V Bus
o
Both buses are also PCI-X 100MHz and PCI 66MHz 3.3V capable, depending upon
the card inserted.
o
PCI specification, revision 2.3 compliant
o
PCI-X 1.0a specification compliant
o
PCI-X 2.0 specification compliant
o
3.3V. Is not 5V tolerant
•
PCI-X 2.0 bus
o
One hot-plug capable slot supporting PCI-X 133MT/s 3.3V/1.5V bus
o
PCI-X 2.0 uses 4 groups of source synchronous signals, each with a strobe pair.
Each group is routed together on the same layer with no layer changes, and length is
matched to the groups’ strobes. A minimum length delta is required between strobes
of the source synchronous groups corresponding with mapping of signals onto the
PCI-X connector. Additional details about source synchronous groups
and their
constraints can be found in the PCI-X 2.0 specification.
•
PCI Express X8 link (2 GB/s each direction, 4 GB/s total)
o
Used for the connection between the PXH and MCH.