Intel® Server Board SE7520BD2 Technical Product SpecificationPlatform Management Architecture
Revision 1.3
Intel Confidential
109
4.6.6 I
2
C Interfaces
The FMM incorporates two master/slave I
2
C interfaces (I
2
C interfaces 0 and 1) and four master-
only I
2
C interfaces (I
2
C interfaces 2, 3, 4 and 5). All I
2
C interfaces can generate an I
2
C clock at a
firmware-programmable rate, with the I
2
C clock rate derived from the FMM master clock.
Programmable values support the standard rates up to a 1 megabit/sec rate, as well as
intermediate and higher clock rates that may be used in particular implementations in which I
2
C
slaves support higher clock rates.
The I
2
C master interface supports 10-bit addressing at the standard I
2
C 10-bit address
locations. This support is accomplished by the interface’s interpretation of the initial address
byte.
All I
2
C interfaces are SMBUS 2.0 compliant.
The master/slave interfaces each have two separate transmit registers. The I
2
C Master Transmit
Data Register is used when the interface acts as a master accessing a slave device. The I
2
C
Slave Transmit Data Register is used to write data to the bus when the interface has been
addressed as a slave to be read from.
The master-only interfaces do not have an I
2
C Slave Transmit Data Register.
The slave interface sections of each of the master/slave interfaces can be configured by FMM
firmware to respond at one, two, or three separate slave addresses.
The I
2
C clock and data inputs to the Sahalee are digitally filtered so that input glitches of less
than four Sahalee clock cycles are rejected. Both high and low polarity glitches are rejected.
This specification defines a transaction as a data transfer bounded by a START and STOP, or
bounded by a START and repeated START. A stream is defined as one or more transactions
bounded by a START and STOP.
There are two types of bus transactions in master mode: Master Transmit and Master Receive.
Master Transmit pertains to writing data to a slave device. Master Receive pertains to reading
from a slave device. The I
2
C interface recognizes the transaction type by sampling bit 0 of
XMIT_DATA when the I
2
C Master Transmit Data Register is written to with the START bit set. If
bit 0 of XMIT_DATA is equal to 0, the transaction is a Master Transmit. If it is equal to 1, the
transaction is a Master Receive.
When in Master Mode, the interface is responsible for generating the I
2
C clock. This is
straightforward when performing a Master Transmit transaction. Each byte written to the I
2
C
Master Transmit Data register results in nine clock cycles on the bus: eight for the data bits, and
one for the ACK/NAK bit.
4.6.7 16550*-style
UARTs
The FMM has two UARTs for serial communication which are 16550* compatible. UART#1 is
used by the EMP interface of the module while UART#2 is used for an ICMB interface.
Note:
The Emergency Management Port (EMP) interface does not use the DSR signal. When
this module is used in conjunction with the 87427 SIO, the module EMP signals are connected
in a null modem fashion to the SIO signals.