Error Reporting and Handling
Intel® Server Board SE7520BD2 Technical Product Specification
134
Revision
1.3
When the hardware detects that a packet is corrupted, a link level retry mechanism is used to
perform a retry of the packet that was corrupted and all the following packets. Although this
interrupts the delivery of packets and slows down communication, it does maintain link integrity.
If it is determined that too many errors have occurred, the hardware may determine that the
quality of the connection is a problem. At this point the devices will enter a quick training
sequence know as recovery. Note that the width of the connection is not renegotiated, but the
adjustment of skew between lanes may occur.
If the hardware is unable to perform a successful recovery as described above, then the link will
automatically revert to the polling state and initiate a full retraining sequence. The occurrence of
a retraining is a drastic event which initiates a reset to the downstream device and all devices
below that and is logged to the MCH as a “link down” error. Although data will be lost and
processes will need to be restarted, it is preferred to taking the system down.
For data packet protection a 32-bit CRC protection scheme is used (smaller link packets use 16-
bit CRC). Also, since packets utilize 8-bit/10-bit encoding and not all encoding is used, further
data protection is provided as illegal codes can be detected.
5.5.3
RAS Features of FSB
The FSB incorporates parity protection for the data pins of the FSB. There is no ECC for FSB
signals.
5.5.4 PCI-X
PCI-X provides two signals for detection and signaling of two kinds of errors. This includes data
parity and system errors.
The first of these is PERR# (parity error reporting), which is used for signaling data parity errors
on all transactions except special cycle transactions.
The second of these is SERR# (system error reporting). SERR# is asserted if the device’s parity
checking logic detects an error in a single address cycle or in either address phase of a dual
address cycle or, as mentioned above, a data parity error is detected during a special cycle
transaction. SERR# may optionally be used to report other internal errors that might impact the
system or data integrity. Note that SERR# will generate a critical system interrupt (non-
maskable interrupt) and is, therefore, fatal.
5.5.4.1
Light Guided Diagnostics*
TBD
5.5.5 RMC
Connector
Utilization
The 8-pin RMC connector provides an interface to server management sensors that a third-
party server management product can query over the SMBus interface. This SMBus is internally
known as the peripheral SMBus.
5.5.5.1 SMBus
Interface
The SMBus devices available are dependent on the platform being used, but share the same 8-
pin connector. It is left to the RMC vendor to properly monitor the sensors on the baseboard as
desired (voltage, fan, temperature, etc.). In addition, this interface can also reset and power