Intel SE7520BD2, Технические характеристики продукции, Страница: 23 / 179

Intel® Server Board SE7520BD2 Technical Product Specification Product Overview
Revision 1.3 Intel Confidential 11
Table 1. Processor Support Matrix
Processor Family Package Type FSB
Frequency
Technology Frequency Cache
Size
Support
Intel® Xeon™ FC-mPGA4 667 MHz 2.8 GHz 1024 KB No
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 2.8 GHz 1024KB Yes
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 3.0 GHz 1024KB Yes
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 3.2 GHz 1024KB Yes
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 3.4 GHz 1024KB Yes
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 3.6 GHz 1024KB Yes
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 3.0 GHz 2048KB Yes **
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 3.2 GHz 2048KB Yes **
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 3.4 GHz 2048KB Yes **
Intel® Xeon™ FC-mPGA4 800 MHz 90 nM 3.6 GHz 2048KB Yes **
Note : ** BIOS P07 or greater is required to support the Intel® Xeon™ processor with 2MB L2
cache.
The Server Board SE7520BD2 is designed to provide up to 120-A per processor. Processors
with higher current requirements are not supported.
2.7.1.1 Mixed Processor Steppings
For optimum system performance, only identical processors should be installed in a system.
Processor steppings can be mixed in a system provided that there is no more than a 1-stepping
difference in all processors installed. If the installed processors are more than 1-stepping apart,
an error (8080 through 8183) is logged in the System Event Log (SEL) and an error (01298000
through 01298003) is reported to the Management Module. Acceptable mixed steppings are not
reported as errors.
2.7.1.2 Mixed Processor Models
Processor models cannot be mixed in a system. If this condition is detected, an error (8196) is
logged in the SEL.
2.7.1.3 Mixed Processor Families
Processor families cannot be mixed in a system. If this condition is detected, an error (8194) is
logged in the SEL.
2.7.1.4 Mixed Processor Cache Sizes
If the installed processors have mixed cache sizes, an error (8192) will be logged in the SEL
and an error (196) is reported to the Management Module. The size of all cache levels must
match between all installed processors. Mixed cache processors are not supported.
2.7.1.5 Microcode
IA-32 processors have the capability of correcting specific errata through the loading of an Intel-
supplied data block (microcode update). The BIOS is responsible for storing the update in
nonvolatile memory and loading it into each processor during POST. The BIOS performs all the
recommended update signature verification prior to storing the update in the Flash.