Product Overview
Intel® Server Board SE7520BD2 Technical Product Specification
20
Revision
1.3
2.9.1.1 PCI
Interface
The ICH5-R PCI interface provides a 33-MHz, Revision 2.3 compliant implementation. All PCI
signals are 5-V tolerant, except PME#. The ICH5 integrates a PCI arbiter that supports up to six
external PCI bus masters in addition to the internal ICH5 requests.
On the Server Board SE7520BD2, this PCI interface is used to support one onboard PCI
device, the ATI Rage XL video controller, and one 5-V PCI 32-bit/33MHz slot.
2.9.1.2
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to two IDE devices providing an interface for IDE hard disks
and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports
PIO IDE transfers up to 16 MB/s and Ultra ATA transfers up 100 MB/s. It does not consume any
ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers. The
ICH5-R’s IDE system contains two independent IDE signal channels; however, the SE7520BD2
board utilizes only one. They can be electrically isolated independently.
On the Server Board SE7520BD2, the primary bus is connected to the legacy IDE connector
2.9.1.3 SATA
Controller
The SATA controller supports two SATA devices providing an interface for SATA hard disks and
ATAPI devices. The SATA interface supports PIO IDE transfers up to 16 Mb/s and Serial ATA
transfers up to 1.5 Gb/s (150 MB/s). The ICH5-R’s SATA system contains two independent
SATA signal ports. They can be electrically isolated independently. Each SATA device can have
independent timings. They can be configured to the standard primary and secondary channels.
The Server Board SE7520BD2 supports two SATA connectors for internal HDD supporting
RAID. The ICH5 SATA RAID has two channels of SATA RAID support. It uses the LSI Logic
SATA RAID stack, which is similar to Intel’s RAID stack. This will allow you have either RAID L
level 0 or 1 support. For the above LSI* 53C1030 integrated SCSI firmware RAID, you only get
one array. Also, in only in one mode RAID 0 (Integrated Striping) or RAID 1/1e (Integrated
Mirroring/Enhanced) will you get one array. The array will not span across channels, all the
array drives need to be on one channel.
2.9.1.4
Low Pin Count (LPC) Interface
The ICH5-R implements an LPC Interface as described in the Low Pin Count Interface
Specification, Revision 1.1. The Low Pin Count (LPC) bridge function of the ICH5 resides in PCI
Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other
functional units including DMA, interrupt controllers, timers, power management, system
management, GPIO, and RTC.
On the Server Board SE7520BD2, the LPC bus is connected from the ICH5-R to both the SIO3
(NSC* PC87427) and the FMM connector.
2.9.1.5
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers.