Intel i960 Jx, Руководство разработчика

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CACHE AND ON-CHIP DATA RAM
4-8
4.5.3 Data Cache Fill Policy
The i960 Jx processor always uses a “natural” fill policy for cacheable loads. The processor
fetches only the amount of data that is requested by a load (i.e., a word, long-word, etc.) on a data
cache miss. Exceptions are byte and short-word accesses, which are always promoted to words.
This allows a complete word to be brought into the cache and marked valid. When the data cache
is disabled and loads are done from a cacheable region, promotions from bytes and short-words
still take place.
4.5.4 Data Cache Write Policy
The write policy determines what happens on cacheable writes (stores). The i960 Jx processor
always uses a write-through policy. Stores are always seen on the external bus, thus maintaining
coherency between the data cache and external memory.
The i960 Jx processor always uses a write-allocate policy for data. For a cacheable location, data is
always written to the data cache regardless of whether the access is a hit or miss. The following
cases are relevant to consider:
1. In the case of a hit for a word or multi-word store, the appropriate line and word(s) are
updated with the data.
2. In the case of a miss for a word or multi-word store, a tag and cache line are allocated, when
needed, and the appropriate valid bits, line, and word(s) are updated.
3. In the case of byte or short-word data that hits a valid word in the cache, both the word in
cache and external memory are updated with the data; the cache word remains valid.
4. In the case of byte or short-word data that falls within a valid line but misses because the
appropriate word is invalid, both the word and external memory are updated with the data;
however, the cache word remains invalid.
5. In the case of byte or short-word data that does not fall within a valid line, the external
memory is updated with the data. For data writes less than a word, the D-cache is not
updated; the tags and valid bits are not changed.
A byte or short-word is always invalid in the D-cache since valid bits only apply to words.
For cacheable stores that are equal to or greater than a word in length, cache tags and appropriate
valid bits are updated whenever data is written into the cache. Consider a word store that misses as
an example. The tag is always updated and its valid bit is set. The appropriate valid bit for that
word is always set and the other three valid bits are always cleared. When the word store hits the
cache, the tag bits remain unchanged. The valid bit for the stored word is set; all other valid bits
are unchanged.