Intel i960 Jx, Руководство разработчика

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TIMERS
10-10
(TMRx.sup)
Timer Register
Supervisor
Write Control
Bit 3
READ
Bit is available 1 bus clock after executing a read instruction from
TMRx.
WRITE
Writing a ‘1’ locks out user mode writes within 1 bus clock after the
store instruction executes to TMRx. Upon detecting a user mode write
the timer generates a TYPE.MISMATCH fault.
(TMRx.csel1:0)
Timer Input
Clock Select
Bits 4-5
READ
Bits are available 1 bus clock after executing a read instruction from
TMRx.csel1:0 bit(s).
WRITE
The timer re-synchronizes the clock cycle used to decrement TCRx
within one bus clock cycle after executing a store instruction to
TMRx.csel1:0 bit(s).
(TCRx.d31:0)
Timer Count
Register
READ
The current TCRx count value is available within 1 bus clock cycle
after executing a read instruction from TCRx. When the timer is
running, the pre-decremented value is returned as the current value.
WRITE
The value written to TCRx becomes the active value within 1 bus
clock cycle. When the timer is running, the value written is
decremented in the current clock cycle.
(TRRx.d31:0)
Timer Reload
Register
READ
The current TRRx count value is available within 1 bus clock after
executing a read instruction from TRRx. When the timer is transferring
the TRRx count into TCRx in the current count cycle, the timer returns
the new TCRx count value to the executing read instruction.
WRITE
The value written to TRRx becomes the active value stored in TRRx
within 1 bus clock cycle. When the timer is transferring the TRRx
value into the TCRx, data written to TRRx is also transferred into
TCRx.
Table 10-5. Timer Responses to Register Bit Settings
(Sheet 2 of 2)
Name Status Action