INDEX
Index-14
subi
6-112
subie
6-109
subig
6-109
subige
6-109
subil
6-109
subile
6-109
subine
6-109
subino
6-109
subio
6-109
subo
6-112
suboe
6-109
subog
6-109
suboge
6-109
subol
6-109
subole
6-109
subone
6-109
subono
6-109
suboo
6-109
subtract
conditional instructions
6-109
integer instruction
6-112
ordinal instruction
6-112
ordinal with carry instruction
6-108
supervisor calls
7-2
supervisor mode resources
3-23
Supervisor Stack
7-17
supervisor stack
3-1
,
3-12
alignment
3-15
supervisor-trace mode
9-3
syncf
6-113
,
8-20
synchronize faults instruction
6-113
sysctl
1-4
,
3-8
,
3-23
,
4-4
,
4-5
,
4-6
,
6-114
,
9-6
,
A-3
system calls
7-2
,
7-15
calls
7-2
system-local
7-2
,
8-2
system-supervisor
7-2
,
8-2
system control instruction
6-114
system procedure table
3-1
,
3-12
,
7-15
alignment
3-15
T
TC
3-23
,
9-2
TCR0, TCR1
10-6
Test Access Port (TAP) controller
15-2
architecture
15-3
Asynchronous Reset Input (TRST) pin
15-5
block diagram
15-3
Serial Test Data Output (TDO) pin
15-5
state diagram
15-4
Test Clock (TCK) pin
15-5
Test Mode Select (TMS) pin
15-5
test features
15-2
test instructions
6-118
Test Mode Select (TMS) line
15-2
teste
6-118
testg
6-118
testge
6-118
testl
6-118
testle
6-118
testne
6-118
testno
6-118
testo
6-118
32-bit bus width byte enable encodings
14-8
32-bit wide data bus bursts
14-12
timer
interrupts
11-9
memory-mapped addresses
10-2
Timer Count Register (TCR0, TCR1)
10-6
Timer Count Register (TCRx)
10-6
address and access type
3-11
Timer Mode Register
timer mode control bit summary
10-8
Timer Mode Register (TMR0, TMR1)
10-3
Timer Mode Register (TMRx)
address and access type
3-11
terminal count
10-4
timer clock encodings
10-6
Timer Reload Register (TRR0, TRR1)
10-7
Timer Reload Register (TRRx)
address and access type
3-11
timers
overview
1-6
TMR0, TMR1
10-3
Trace Controls (TC) Register
3-23
,
9-2
Trace Controls (TC) register
3-23
,
9-2
trace events
9-1
hardware breakpoint registers
9-1
Содержание i960 Jx
Страница 1: ...Release Date December 1997 Order Number 272483 002 i960 Jx Microprocessor Developer s Manual ...
Страница 24: ......
Страница 25: ...1 INTRODUCTION ...
Страница 26: ......
Страница 35: ...2 DATA TYPES AND MEMORY ADDRESSING MODES ...
Страница 36: ......
Страница 46: ......
Страница 47: ...3 PROGRAMMING ENVIRONMENT ...
Страница 48: ......
Страница 73: ...4 CACHE AND ON CHIP DATA RAM ...
Страница 74: ......
Страница 85: ...5 INSTRUCTION SET OVERVIEW ...
Страница 86: ......
Страница 111: ...6 INSTRUCTION SET REFERENCE ...
Страница 112: ......
Страница 195: ...INSTRUCTION SET REFERENCE 6 83 6 Opcode mov 5CCH REG movl 5DCH REG movt 5ECH REG movq 5FCH REG See Also LOAD STORE lda ...
Страница 233: ...7 PROCEDURE CALLS ...
Страница 234: ......
Страница 256: ......
Страница 257: ...8 FAULTS ...
Страница 258: ......
Страница 291: ...9 TRACING AND DEBUGGING ...
Страница 292: ......
Страница 309: ...10 TIMERS ...
Страница 310: ......
Страница 324: ......
Страница 325: ...11 INTERRUPTS ...
Страница 326: ......
Страница 369: ...12 INITIALIZATION AND SYSTEM REQUIREMENTS ...
Страница 370: ......
Страница 412: ......
Страница 413: ...13 MEMORY CONFIGURATION ...
Страница 414: ......
Страница 429: ...14 EXTERNAL BUS ...
Страница 430: ......
Страница 468: ......
Страница 469: ...15 TEST FEATURES ...
Страница 470: ......
Страница 493: ...A CONSIDERATIONS FOR WRITING PORTABLE CODE ...
Страница 494: ......
Страница 502: ......
Страница 503: ...B OPCODES AND EXECUTION TIMES ...
Страница 504: ......
Страница 515: ...C MACHINE LEVEL INSTRUCTION FORMATS ...
Страница 516: ......
Страница 523: ...D REGISTER AND DATA STRUCTURES ...
Страница 524: ......
Страница 550: ......
Страница 551: ...GLOSSARY ...
Страница 552: ......
Страница 561: ...INDEX ...
Страница 562: ......
Страница 578: ......