INSTRUCTION SET REFERENCE
6-104
6.2.62
STORE
Mnemonic:
st
Store
stob
Store Ordinal Byte
stos
Store Ordinal Short
stib
Store Integer Byte
stis
Store Integer Short
stl
Store Long
stt
Store Triple
stq
Store Quad
Format:
st*
src1,
dst
reg
mem
Description:
Copies a byte or group of bytes from a register or group of registers to
memory. src specifies a register or the first (lowest numbered) register of
successive registers.
dst specifies the address of the memory location where the byte or first byte
or a group of bytes is to be stored. The full range of addressing modes may be
used in specifying dst. Refer to
section 2.3, “MEMORY ADDRESSING
MODES” (pg. 2-6)
for a complete discussion.
stob
and
stib
store a byte and
stos
and
stis
store a half word from the src
register’s low order bytes. Data for ordinal stores is truncated to fit the
destination width. When the data for integer stores cannot be represented
correctly in the destination width, an Arithmetic Integer Overflow fault is
signaled.
st
,
stl
,
stt
and
stq
copy 4, 8, 12 and 16 bytes, respectively, from successive
registers to memory.
For
stl
, src must specify an even numbered register (e.g., g0, g2, ... or r0, r2,
...). For
stt
and
stq
, src must specify a register number that is a multiple of
four (e.g., g0, g4, g8, ... or r0, r4, r8, ...).
Action:
st:
if (illegal_write_to_on_chip_RAM)
generate_fault(TYPE.MISMATCH);
else if ((effective_address[1:0] !=
00
2
) && unaligned_fault_enabled)
{store_to_memory(effective_address)[31:0]
=
src1;
generate_fault(OPERATION.UNALIGNED);}
else
store_to_memory(effective_address)[31:0] = src1;
Содержание i960 Jx
Страница 1: ...Release Date December 1997 Order Number 272483 002 i960 Jx Microprocessor Developer s Manual ...
Страница 24: ......
Страница 25: ...1 INTRODUCTION ...
Страница 26: ......
Страница 35: ...2 DATA TYPES AND MEMORY ADDRESSING MODES ...
Страница 36: ......
Страница 46: ......
Страница 47: ...3 PROGRAMMING ENVIRONMENT ...
Страница 48: ......
Страница 73: ...4 CACHE AND ON CHIP DATA RAM ...
Страница 74: ......
Страница 85: ...5 INSTRUCTION SET OVERVIEW ...
Страница 86: ......
Страница 111: ...6 INSTRUCTION SET REFERENCE ...
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Страница 195: ...INSTRUCTION SET REFERENCE 6 83 6 Opcode mov 5CCH REG movl 5DCH REG movt 5ECH REG movq 5FCH REG See Also LOAD STORE lda ...
Страница 233: ...7 PROCEDURE CALLS ...
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Страница 256: ......
Страница 257: ...8 FAULTS ...
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Страница 291: ...9 TRACING AND DEBUGGING ...
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Страница 309: ...10 TIMERS ...
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Страница 325: ...11 INTERRUPTS ...
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Страница 369: ...12 INITIALIZATION AND SYSTEM REQUIREMENTS ...
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Страница 413: ...13 MEMORY CONFIGURATION ...
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Страница 429: ...14 EXTERNAL BUS ...
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Страница 469: ...15 TEST FEATURES ...
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Страница 493: ...A CONSIDERATIONS FOR WRITING PORTABLE CODE ...
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Страница 502: ......
Страница 503: ...B OPCODES AND EXECUTION TIMES ...
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Страница 515: ...C MACHINE LEVEL INSTRUCTION FORMATS ...
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Страница 523: ...D REGISTER AND DATA STRUCTURES ...
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Страница 551: ...GLOSSARY ...
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Страница 561: ...INDEX ...
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