TEST FEATURES
15-11
15
If TMS is high on the rising edge of TCK, the controller enters the Exit1-DR. If TMS is low on the
rising edge of TCK, the controller enters the Shift-DR state.
15.3.5.5
Shift-DR State
In this controller state, the test data register, which is connected between TDI and TDO as a result
of the current instruction, shifts data one bit position nearer to its serial output on each rising edge
of TCK. Test data registers that the current instruction selects but does not place in the serial path,
retain their previous value during this state.
The instruction does not change while the TAP controller is in this state.
If TMS is high on the rising edge of TCK, the controller enters the Exit1-DR state. If TMS is low
on the rising edge of TCK, the controller remains in the Shift-DR state.
15.3.5.6
Exit1-DR State
This is a temporary controller state. When the TAP controller is in the Exit1-DR state and TMS is
held high on the rising edge of TCK, the controller enters the Update-DR state, which terminates
the scanning process. If TMS is held low on the rising edge of TCK, the controller enters the
Pause-DR state.
The instruction does not change while the TAP controller is in this state. All test data registers
selected by the current instruction retain their previous value during this state.
15.3.5.7
Pause-DR State
The Pause-DR state allows the test controller to temporarily halt the shifting of data through the
test data register in the serial path between TDI and TDO. The test data register selected by the
current instruction retains its previous value during this state. The instruction does not change in
this state.
The controller remains in this state as long as TMS is low. When TMS goes high on the rising edge
of TCK, the controller moves to the Exit2-DR state.
15.3.5.8
Exit2-DR State
This is a temporary state. If TMS is held high on the rising edge of TCK, the controller enters the
Update-DR state, which terminates the scanning process. If TMS is held low on the rising edge of
TCK, the controller enters the Shift-DR state.
The instruction does not change while the TAP controller is in this state. All test data registers
selected by the current instruction retain their previous value during this state.
Содержание i960 Jx
Страница 1: ...Release Date December 1997 Order Number 272483 002 i960 Jx Microprocessor Developer s Manual ...
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Страница 25: ...1 INTRODUCTION ...
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Страница 35: ...2 DATA TYPES AND MEMORY ADDRESSING MODES ...
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Страница 47: ...3 PROGRAMMING ENVIRONMENT ...
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Страница 73: ...4 CACHE AND ON CHIP DATA RAM ...
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Страница 85: ...5 INSTRUCTION SET OVERVIEW ...
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Страница 111: ...6 INSTRUCTION SET REFERENCE ...
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Страница 195: ...INSTRUCTION SET REFERENCE 6 83 6 Opcode mov 5CCH REG movl 5DCH REG movt 5ECH REG movq 5FCH REG See Also LOAD STORE lda ...
Страница 233: ...7 PROCEDURE CALLS ...
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Страница 257: ...8 FAULTS ...
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Страница 291: ...9 TRACING AND DEBUGGING ...
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Страница 309: ...10 TIMERS ...
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Страница 325: ...11 INTERRUPTS ...
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Страница 369: ...12 INITIALIZATION AND SYSTEM REQUIREMENTS ...
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Страница 413: ...13 MEMORY CONFIGURATION ...
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Страница 429: ...14 EXTERNAL BUS ...
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Страница 469: ...15 TEST FEATURES ...
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Страница 493: ...A CONSIDERATIONS FOR WRITING PORTABLE CODE ...
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Страница 503: ...B OPCODES AND EXECUTION TIMES ...
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Страница 515: ...C MACHINE LEVEL INSTRUCTION FORMATS ...
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Страница 523: ...D REGISTER AND DATA STRUCTURES ...
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Страница 551: ...GLOSSARY ...
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Страница 561: ...INDEX ...
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