Intel 810A3, Руководство по конструкции

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SC242 Processor Design Guidelines
3-4 Intel
®
810A3 Chipset Design Guide
3.4 Minimizing Crosstalk
The following general rules will minimize the impact of crosstalk in the high speed AGTL+ bus
design:
The following general rules will minimize the impact of crosstalk in the high speed AGTL+ bus
design:
•
Maximize the space between traces. Maintain a minimum of 0.010” between traces wherever
possible. It may be necessary to use tighter spacings when routing between component pins.
•
Avoid parallelism between signals on adjacent layers.
•
Since AGTL+ is a low signal swing technology, it is important to isolate AGTL+ signals from
other signals by at least 0.025”. This will avoid coupling from signals that have larger voltage
swings, such as 5V PCI.
•
Select a board stack-up that minimizes the coupling between adjacent signals.
•
Route AGTL+ address, data and control signals in separate groups to minimize crosstalk
between groups. The Pentium
III processor uses a split transaction bus. In a given clock cycle,
the address lines and corresponding control lines could be driven by a different agent than the
data lines and their corresponding control lines.
3.5 Motherboard Layout Rules for Non-AGTL+ (CMOS)
Signals
Non-AGTL+ (CMOS) Signals
Route these signals on any layer or any combination of layers.
Table 3-6. Routing Guidelines for Non-AGTL+ Signals
Signal Trace Width Spacing to Other Traces Trace Length
A20M# 5 mils 10 mils 1” to 9”
FERR# 5 mils 10 mils 1” to 9”
FLUSH# 5 mils 10 mils 1” to 9”
IERR# 5 mils 10 mils 1” to 9”
IGNNE# 5 mils 10 mils 1” to 9”
INIT# 5 mils 10 mils 1” to 9”
THERMTRIP# 5 mils 10 mils 1” to 9”
LINT[0] (INTR) 5 mils 10 mils 1” to 9”
LINT[1] (NMI) 5 mils 10 mils 1” to 9”
PWRGOOD 5 mils 10 mils 1” to 9”
SLP# 5 mils 10 mils 1” to 9”
PICD[1:0] 5 mils 10 mils 1” to 8”
PREQ# 5 mils 10 mils 1” to 9”
SMI 5 mils 10 mils 1” to 9”
STPCLK# 5 mils 10 mils 1” to 9”