Intel 810A3, Руководство по конструкции

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viii Intel
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810A3 Chipset Design Guide
Tables
2-1 Platform Pin Definition Comparison for Single Processor Designs ..............2-2
2-2 Processor Pin Definition Comparison ...........................................................2-3
2-3 Intel
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Pentium
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III Processor and GMCH AGTL+ Parameters for
Example Calculations ...................................................................................2-4
2-4 Example T
FLT_MIN
Calculations FOR 100 MHz Bus .....................................2-5
2-5 Example T
FLT_MIN
Calculations (Frequency Independent)...........................2-5
2-6 Segment Descriptions and Lengths for Figure 2-1 .......................................2-6
2-7 Trace Width (Space Guidelines)...................................................................2-6
2-8 Routing Guidelines for Non-AGTL+ Signals .................................................2-8
2-9 Example Resistor Values for CLKREF Divider Circuit (3.3V Source).........2-10
3-1 Intel
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Pentium
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III Processor and GMCH AGTL+ Parameters for
Example Calculations ...................................................................................3-1
3-2 Example T
FLT_MAX
Calculations for 100 MHz Bus .......................................3-2
3-3 Example T
FLT_MIN
Calculations (Frequency Independent)...........................3-2
3-4 Segment Descriptions and Lengths for Figure 3-2 ......................................3-3
3-5 Trace Width:Space Guidelines .....................................................................3-3
3-6 Routing Guidelines for Non-AGTL+ Signals .................................................3-4
4-1 System Memory Routing ..............................................................................4-5
4-2 Display Cache Routing (Topology 1) ............................................................4-8
4-3 Display Cache Routing (Topology 2) ............................................................4-8
4-4 Display Cache Routing (Topology 3) ............................................................4-8
4-5 Display Cache Routing (Topology 4) ............................................................4-9
4-6 AC’97 Configuration Combinations.............................................................4-18
4-7 Recommended USB Trace Characteristics ................................................4-23
4-8 Inductor.......................................................................................................4-30
4-9 Capacitor ....................................................................................................4-30
4-10 Resistor.......................................................................................................4-30
4-11 DPLL LC Filter Component Example..........................................................4-37
4-12 Additional DPLL LC Filter Component Example .........................................4-38
4-13 Resistance Values for Frequency Response Curves (see Figure 4-38 ).....4-39
5-1 Trace Width Space Guidelines .....................................................................5-6
5-2 Host Clock Routing .......................................................................................5-6
6-1 Intel
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810A3 Chipset Clocks.........................................................................6-1
6-2 Group Skew and Jitter Limits at the Pins of the Clock Chip .........................6-3
6-3 Signal Group and Resistor............................................................................6-3
6-4 Layout Dimensions .......................................................................................6-4
7-1 Intel
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810A3 Chipset Power Map .................................................................7-3
7-2 Intel
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810A3 Chipset Voltage Regulator Specifications ...............................7-4
7-3 Power Sequencing Timing Definitions ........................................................7-12
8-1 AGTL+ Connectivity Checklist for 370-Pin Socket Processors.....................8-2
8-2 CMOS Connectivity Checklist for 370-Pin Socket Processors .....................8-3
8-3 TAP Checklist for a 370-Pin Socket Processor ...........................................8-3
8-4 Miscellaneous Checklist for 370-Pin Socket Processors ..............................8-4
8-5 AGTL+ Connectivity Checklist for SC242 Processors ..................................8-5
8-6 CMOS Connectivity Checklist for SC242 Processors...................................8-6
8-7 TAP Checklist for SC242 Processors ...........................................................8-6
8-8 Miscellaneous Checklist for SC242 Processors ...........................................8-6
8-9 Special Consideration Checklist ...................................................................8-7
8-10 Clock Generator Checklist ............................................................................8-7