Intel 810A3, Руководство по конструкции

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Layout and Routing Guidelines
4-20 Intel
®
810A3 Chipset Design Guide
Clocking is provided from the primary codec on the link via BITCLK, and is derived from a
24.576 MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator
requirements. BITCLK is a 12.288 MHz clock driven by the primary codec to the digital controller
(ICH), and any other codec present. That clock is used as the timebase for latching and driving
data.
The ICH supports wake on ring from S1-S4 via the AC’97 link. The codec asserts SDATAIN to
wake the system. To provide wake capability and/or caller ID, standby power must be provided to
the modem codec.
If no codec is attached to the link, internal pulldowns will prevent the inputs from floating;
therefore, external resistors are not required.
Figure 4-22. Tee Topology AC'97 Trace Length Requirements for ATX
Figure 4-23. Daisy-Chain Topology AC'97 Trace Length Requirements for ATX
I C H
C o d e c
A
M
R
4 " M a x
2 " M a x 3 " M a x
I C H C o d e c
A
M
R
5" Max 3" Max