Intel 810A3, Руководство по конструкции

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Intel
®
810A3 Chipset Design Guide 5-3
Advanced System Bus Design
There are multiple cases to consider. Note that while the same trace connects two components,
component A and component B, the minimum and maximum flight time requirements for
component A driving component B as well as component B driving component A must be met. The
cases to be considered are:
•
Processor driving processor
•
Processor driving chipset
•
Chipset driving processor
A designer using components other than those listed above must evaluate additional combinations
of driver and receiver.
5.1.2 Determine General Topology, Layout, and Routing Desired
After calculating the timing budget, determine the approximate location of the processor and the
chipset on the base board.
5.1.3 Pre-Layout Simulation
5.1.3.1 Methodology
Analog simulations are recommended for high speed system bus designs. Start simulations prior to
layout. Pre-layout simulations provide a detailed picture of the working “solution space” that meets
flight time and signal quality requirements. The layout recommendations in the previous sections
are based on pre-layout simulations conducted at Intel. By basing board layout guidelines on the
solution space, the iterations between layout and post-layout simulation can be reduced.
Intel recommends running simulations at the device pads for signal quality and at the device pins
for timing analysis. However, simulation results at the device pins may be used later to correlate
simulation performance against actual system measurements.
5.1.3.2 Sensitivity Analysis
Pre-layout analysis includes a sensitivity analysis using parametric sweeps. Parametric sweep
analysis involves varying one or two system parameters while all others such as driver strength,
package, Z
0
, and S
0
are held constant. This way, the sensitivity of the proposed bus topology to
varying parameters can be analyzed systematically. Sensitivity of the bus to minimum flight time,
maximum flight time, and signal quality should be covered. Suggested sweep parameters include
trace lengths, termination resistor values, and any other factors that may affect flight time, signal
quality, and feasibility of layout. Minimum flight time and worst signal quality are typically
analyzed using fast I/O buffers and interconnect. Maximum flight time is typically analyzed using
slow I/O buffers and slow interconnects.
Outputs from each sweep should be analyzed to determine which regions meet timing and signal
quality specifications. To establish the working solution space, find the common space across all
the sweeps that result in passing timing and signal quality. The solution space should allow enough
design flexibility for a feasible, cost-effective layout.