Intel 810A3, Руководство по конструкции, Страница: 131 / 166

Intel
®
810A3 Chipset Design Guide 7-7
System Design Considerations
7.2.3 82810A3 GMCH Decoupling Guidelines
GMCH Vsus 3.3V (3.3V Standby) Power Plane Decoupling
•
3.3V Droop Specification
— Worse case droop on 3.3V plane must not go below 2.5 V.
— Droop below the minimum Vcc of 3.135 V must not occur for a period greater than 2ns.
•
Place four 0.01
µ
F decoupling capacitors as close as possible to GMCH.
— Trace from cap pad to via < 500 mils (Ideal = 300 mils).
— Trace width at least 15 mils.
•
Use power vias (multiple if possible).
— Power via example: 18 mil drill, 33–38 mil width.
•
Place capacitors orientation such that flight time will be minimized.
— Vias between GMCH ball and cap pad (see Figure 7-2 ).
The use of top-side (component side) capacitors near the GMCH (as shown in Figure 7-2 ) as the
only means of decoupling the VSUS_3.3 V power plane may be insufficient to meet the 3.3V
droop specification or to attenuate noise. In some cases bottom-side (solder side) capacitors
(connected at three to four of the VSUS_3.3 V signal balls to the nearest VSS balls) may be
required to comply with the droop specification and improve noise protection. This is important in
platforms where 100 MHz or 133 MHz SDRAM interfaces are used.
Power Plane Layout
•
Make the power planes as square as possible with no sharp corners.
•
Avoid crossing traces over multiple power planes.