Intel 810A3, Руководство по конструкции

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Clocking
6-2 Intel
®
810A3 Chipset Design Guide
6.2 Clock Architecture
Figure 6-1. Intel

810A3 Chipset Clock Architecture
clk_arch.vsd
52
55
50
49
CPU_2_ITP
APIC_0
C P U _ 1
C P U _ 0
2.5V
Clock Synthesizer
P W R D W N
S E L 1
S E L 0
S D A T A
S C L K
S D R A M 0
S D R A M 1
S D R A M 2
S D R A M 3
S D R A M 4
S D R A M 5
S D R A M 6
S D R A M 7
D C L K
32
29
28
30
31
46
45
43
42
40
39
37
36
34
Main Memory
2 DIMMS
ITP Processor
G M C H
Data
Address
Control
3.3V
3V66_0
U S B _ 0
14.3118 MHz
7
25
3V66_1
R E F
PCIO/ICH
U S B 1
APIC1
8
1
11
26
54
ICH/ICH0
SIO
PCI Total of 6 devices
(
µ
ATX)
(5 slots + 1 down)
32.768 KHz
Dot Clock
12
PCI_1
13
15
16
18
19
20
PCI_2
PCI_3
PCI_4
PCI_5
PCI_6
PCI_7
2.5V
3.3V