Intel 810A3, Руководство по конструкции

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Intel
®
810A3 Chipset Design Guide 2-7
PGA370 Processor Design Guidelines
2.2.2.2 Motherboard Layout Rules for AGTL+ Signals
Minimizing Crosstalk
The following general rules will minimize the impact of crosstalk in the high speed AGTL+ bus
design:
•
Maximize the space between traces. Maintain a minimum of 0.010” between traces wherever
possible. It may be necessary to use tighter spacings when routing between component pins.
•
Avoid parallelism between signals on adjacent layers.
•
Since AGTL+ is a low signal swing technology, it is important to isolate AGTL+ signals from
other signals by at least 0.025”. This will avoid coupling from signals that have larger voltage
swings, such as 5V PCI.
•
Select a board stack-up that minimizes the coupling between adjacent signals.
•
Route AGTL+ address, data and control signals in separate groups to minimize crosstalk
between groups. The Pentium
III processor uses a split transaction bus. In a given clock cycle,
the address lines and corresponding control lines could be driven by a different agent than the
data lines and their corresponding control lines.
Additional Considerations
•
Distribute V
TT
with a wide trace. A 0.050” minimum trace is recommended to minimize DC
losses. Route the V
TT
trace to all components on the host bus. Be sure to include decoupling
capacitors. Guidelines for V
TT
distribution and decoupling are contained in “Slot 1 Processor
Power Distribution Guidelines.”
•
Place resistor divider pairs for V
REF
generation at the MCH component. No V
REF
generation
is needed at the processor(s). V
REF
is generated locally on the processor. Be sure to include
decoupling capacitors. Guidelines for V
REF
distribution and decoupling are contained in “Slot
1 Processor Power Distribution Guidelines.”
•
Special Case AGTL+ signals for simulation: There are six AGTL+ signals that can be driven
by more than one agent simultaneously. These signals may require extra attention during the
layout and validation portions of the design. When a signal is asserted (driven low) by two
agents on the same clock edge, the two falling wave fronts will meet at some point on the bus.
This can create a large undershoot, followed by ringback which may violate the ringback
specifications. This “wired-OR” situation should be simulated for the following signals:
AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM#.