Intel 810A3, Руководство по конструкции

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Design Checklist
8-16 Intel
®
810A3 Chipset Design Guide
8.3 RTC
Guidelines to minimize ESD events that may cause loss of CMOS contents:
•
Provide a 1 uF 805 X5R dielectric, monolithic, ceramic capacitor on the VCCRTC pin. This
capacitor connection should not be stubbed off the trace run and should be as close as possible
to the ICH. If a stub is required, it should be kept to a few mm maximum length. The ground
connection should be made through a via to the plane with no trace between the capacitor pad
and the via.
•
Place the battery, 1K ohm series current limit resistor, and the common-cathode isolation diode
very close to the ICH. If this is not possible, place the common-cathode diode and the 1K ohm
resistor as close to the 1
µ
F cap as possible. Do not place these components between the cap
and the ICH. The battery can be placed remotely from the ICH.
•
On boards that have chassis-intrusion utilizing inverters powered by the VCCRTC pin, place
the inverters as close to the common-cathode diode as possible. If this is not possible, keep the
trace run near the center of the board.
•
Keep the ICH VCCRTC trace away from the board edge. If this trace must run from opposite
ends of the board, keep the trace run towards the board center, away from the board edge
where contact could be made by those handling the board.
8.4 Power Management Signals
•
A power button is required by the ACPI specification.
•
PWRBTN# is connected to the front panel on/off power button. The ICH integrates 16 msec
debouncing logic on this pin.
•
AC power loss circuitry has been integrated into the ICH to detect power failure.
•
It is recommended that the PS_POK signal from the power supply connector be routed through
a Schmitt trigger to square-off and maintain its signal integrity, and not be connected directly
to logic on the board.
•
PS_POK logic from the power supply connector can be powered from the core voltage supply.
•
RSMRST# logic should be powered by a standby supply, making sure that the input to the ICH
is at a 3V level. The RSMST# signal requires a minimum time delay of 1 ms from the rising
edge of the standby power supply voltage. A Schmitt trigger circuit is recommended to drive
the RSMRST# signal. To provide the required rise time, the 1 ms delay should be placed
before the Schmitt trigger circuit. The reference design implements a 20 ms delay at the input
of the Schmitt trigger to ensure the Schmitt trigger inverters have sufficiently powered up
before switching the input. Also ensure that voltage on RSMRST# does not exceed
VCC(RTC).
•
It is recommended that 3.3V logic be used to drive RSMRST# to alleviate rise time problems
when using a resistor divider from VCC5.
•
The PWROK signal to the chipset is a 3V signal.
•
The core well power valid to PWROK asserted at the chipset is a minimum of 1 msec.
•
PWROK to the chipset must be deasserted after RSMRST#.