Intel 810A3, Руководство по конструкции

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Intel
®
810A3 Chipset Design Guide 6-3
Clocking
6.3 Clock Routing Guidelines
Table 6-2 shows the group skew and jitter limits.
Table 6-3 shows the Signal Group and Resistor Tolerance.
Table 6-4 shows the layout dimensions for the clock routing.
Note: All the clock signals must be routed on the same layer which reference to a ground plane.
Table 6-2. Group Skew and Jitter Limits at the Pins of the Clock Chip
Signal Group Pin-Pin Skew Cycle-Cycle Jitter Nominal Vdd
Skew, jitter
measure point
CPU 175 pS 250 pS 2.5V 1.25V
SDRAM 250 pS 250 pS 3.3V 1.50V
APIC 250 pS 500 pS 2.5V 1.25V
48 MHz 250 pS 500 pS 3.3V 1.50V
3V66 175 pS 500 pS 3.3V 1.50V
PCI 500 pS 500 pS 3.3V 1.50V
REF N/A 1000 pS 3.3V 1.50V
Table 6-3. Signal Group and Resistor
Signal Group Resistor
CPU 33
Ω ±
5%
SDRAM/DCLK 22
Ω ±
5%
3V66 22
Ω ±
5%
PCI 33
Ω ±
5%
TCLK 22
Ω ±
5%
OCLK/RCLK 33
Ω ±
5%
48 MHz 33
Ω ±
5%
APIC 33
Ω ±
5%
REF 10
Ω ±
5%