Intel 810A3, Руководство по конструкции

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Clocking
6-4 Intel
®
810A3 Chipset Design Guide
NOTE:
1. X and Y trace lengths are arbitrary. Simulations were performed with each X=2", 4", and 6.”
2. The DCLKREF signal from the external clock synthesizer to the GMCH is a 48 MHz signal. This signal has
no length requirements except those specified in this table. However, care in routing this signal relative to the
DIMM slots is important. Future board designs should attempt to route the DCLKREF trace so that the trace
is not parallel to the DIMM slots or does not pass underneath the DIMM slots. This prevents noise coupling of
memory-related signals into the 48 MHz clock signal.
Table 6-4. Layout Dimensions
Group Receiver Resistor Cap
Topolog
y
A B C D
SDRAM DIMM 22
Ω
N/A Layout 1 0.5” X N/A N/A
CPU
Segment C
=> PPGA
Segment D
=> GMCH
33
Ω
N/A Layout 5 0.1” 0.5” X+4.1 X+5.55”
DCLK
2
GMCH 22
Ω
22 pf Layout 3 0.5” X+2.4” 0.5” N/A
3V66 GMCH 22
Ω
18 pF Layout 3 0.5” X+0.8” 0.5” N/A
3V66 ICH 22
Ω
18 pF Layout 3 0.5” X+0.8” 0.5” N/A
PCI PCI device 33
Ω
N/A Layout 1 0.5”
X+3.85” to
X+10.1”
N/A N/A
PCI PCI socket 33
Ω
N/A Layout 4 0.5”
X+0.4” to
X+6.85”
N/A N/A
PCI ICH 33
Ω
N/A Layout 1 0.5” X+4.0” N/A N/A
TCLK SDRAM 22
Ω
N/A Layout 6 0.5” 1.5” to 2.5”
0.75” to
1.25”
N/A
OCLK/RCLK GMCH 33
Ω
N/A Layout 1 0.5” 3.25” to 3.75” N/A N/A
APIC PPGA 33
Ω
N/A Layout 4 0.5” Y N/A N/A
APIC ICH 33
Ω
N/A Layout 1 0.5” Y+2.4” N/A N/A