Intel 810A3, Руководство по конструкции

Страница: 100 / 166

Advanced System Bus Design
5-6 Intel
®
810A3 Chipset Design Guide
interference from AGTL+ signals in a particular group to AGTL+ signals in a different group. An
example of AGTL+ to non-AGTL+ cross-talk is when CMOS and AGTL+ signals interfere with
each other.
The spacing between the various bus agents causes variations in trunk impedance and stub
locations. These variations cause reflections that can cause constructive or destructive interference
at the receivers. A reduction of noise may be obtained by a minimum spacing between the agents.
Unfortunately, tighter spacing results in reduced component placement options and lower hold
margins. Therefore, adjusting the inter-agent spacing may be one way to change the network’s
noise margin, but mechanical constraints often limit the usefulness of this technique. Always be
sure to validate signal quality after making any changes in agent locations or changes to inter-agent
spacing.
There are six AGTL+ signals that can be driven by more than one agent simultaneously. These
signals may require more attention during the layout and validation portions of the design. When a
signal is asserted (driven low) by two or more agents on the same clock edge, the two falling edge
wave fronts will meet at some point on the bus and can sum to form a negative voltage. The ring-
back from this negative voltage can easily cross into the overdrive region. The signals are AERR#,
BERR#, BINIT#, BNR#, HIT#, and HITM#.
This document addresses AGTL+ layout for both 1 and 2-way 133 MHz/100 MHz processor/
Intel
®
810A3 chipset systems. Power distribution and chassis requirements for cooling, connector
location, memory location, etc., may constrain the system topology and component placement
location; therefore, constraining the board routing. These issues are not directly addressed in this
document.
Section 1.1.2, “References” on page 1-7 contains a listing of several documents that
address some of these issues.
5.1.4.3 Host Clock Routing
Host clock nets should be routed as point-to-point connections through a series resistor placed as
close to the output pins of the clock driver as possible. The value of the series resistor is dependent
on the clock driver characteristic impedance. However, a value of 33
Ω
is a good starting point.
Table 5-2 provides the trace length recommendations for this topology. “H” indicates the length of
the host clock trace starting from the clock driver output pin and ending at the SC242 connector
BCLK pin. Note that the clock route from the clock driver to the GMCH will require an additional
trace length of approximately 4.6” to compensate for the additional propagation delay along the
processor host clock path (SC242 connector plus processor cartridge trace). This value of 4.6”
assumes a propagation speed of 180 ps/in.
Table 5-1. Trace Width Space Guidelines
Cross-talk Type Trace Width:Space Ratio
Intragroup AGTL+ (same group AGTL+) 5:10 or 6:12
Intergroup AGTL+ (different group AGTL+) 5:15 or 6:18
AGTL+ to non-AGTL+ 5:20 or 6:24
Table 5-2. Host Clock Routing
Clock Net Trace length
Clock driver to SC242 connector H
Clock driver to GMCH
H + (clock delay from the processor edge to core) +
connector delay