Intel 810A3, Руководство по конструкции

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PGA370 Processor Design Guidelines
2-6 Intel
®
810A3 Chipset Design Guide
2.2.2.1 Determine General Topology and Layout
In the SET (Single Ended Termination) topology for the 370-pin socket (PGA370), the termination
should be placed close to the processor on the motherboard. There is no termination present at the
chipset end of the network. Due to the lack of termination, SET will exhibit much more ringback
than the dual terminated topology. Extra care is required in SET simulations to make sure that the
ringback specs are met under the worst case signal quality conditions. Intel

810A3 chipset
designs require all AGTL+ signals to be terminated with a 56
Ω
termination on the motherboard.
To ensure processor signal integrity requirements it is highly recommended that all system bus
signal segments to be referenced to the ground plane for the entire route (
Chapter 5,
“Advanced System Bus Design” for details).
NOTES:
1. All AGTL+ bus signals should be referenced to the ground plane for the entire route. See Chapter 5,
“Advanced System Bus Design” .
•
AGTL+ signals should be routed with trace lengths within the range specified for L1+L2 from
the processor pin to the chipset.
•
Use an intragroup AGTL+ spacing to line width to dielectric thickness ratio of at least 2:1:1
for microstrip geomety. If
ε
r
= 4.5, this should limit coupling to 3.4%. For example, intragroup
AGTL+ routing could use 10 mil spacing, 5 mil traces, and a 5 mil prepreg between the signal
layer and the plane it references (assuming a 4-layer motherboard design).
•
The trace width is recommended to be 5 mils and not greater than 6 mils.
Table 2-7 contains the trace width:space ratios assumed for this topology. The crosstalk cases
considered in this guideline involve three types: Intragroup AGTL+, Intergroup AGTL+, and
AGTL+ to non-AGTL+. Intragroup AGTL+ crosstalk involves interference between AGTL+
signals within the same group. Intergroup AGTL+ crosstalk involves interference from AGTL+
signals in a particular group to AGTL+ signals in a different group. An example of AGTL+ to non-
AGTL+ crosstalk is when CMOS and AGTL+ signals interfere with each other.
Figure 2-1. Topology for 370-Pin Socket Designs with Single Ended Termination (SET)
Table 2-6. Segment Descriptions and Lengths for Figure 2-1
1
Segment Description Min length (inches) Max length (inches)
L1 + L2 GMCH to Rtt Stub 1.90 4.50
L2 PGA370 Pin to Rtt stub 0.0 0.20
L3 Rtt Stub length 0.50 2.50
G M C H
P G A 3 7 0
Socket
L(1): Z
0
=60
Ω
±15%.
Vtt
56
Ω
L 2
L 3
L 1
Table 2-7. Trace Width (Space Guidelines)
Crosstalk Type Trace Width:Space Ratios
Intragroup AGTL+ signals (same group AGTL+) 5:10 or 6:12
Intergroup AGTL+ signals (different group AGTL+) 5:15 or 6:18
AGTL+ to non-AGTL+ processor signals 5:20 or 6:24