3-43
BUS INTERFACE UNIT
The major factors that influence bus latency are listed below (in order from longest delay to short-
est delay).
1. Bus Not Ready — As long as the bus remains not ready, a bus hold request cannot be
serviced.
2. Locked Bus Cycle — As long as LOCK remains asserted, a bus hold request cannot be
serviced. Performing a locked move string operation can take several thousands of clocks.
3. Completion of Current Bus Cycle — A bus hold request cannot be serviced until the
current bus cycle completes. A bus hold request will not separate bus cycles required to
move odd-aligned word data. Also, bus cycles with long wait states will delay the
servicing of a bus hold request.
4. Interrupt Acknowledge Bus Cycle — A bus hold request is not serviced until after an
INTA bus cycle has completed. An INTA bus cycle drives LOCK active.
5. DMA and Refresh Bus Cycles — A bus hold request is not serviced until after the DMA
request or refresh bus cycle has completed. Refresh bus cycles have a higher priority than
hold bus requests. A bus hold request cannot separate the bus cycles associated with a
DMA transfer (worst case is an odd-aligned transfer, which takes four bus cycles to
complete).
3.7.1.2
Refresh Operation During a Bus HOLD
Under normal operating conditions, once HLDA has been asserted it remains asserted until
HOLD is removed. However, when a refresh bus request is generated, the HLDA output is re-
moved (driven low) to signal the need for the BIU to regain control of the local bus. The BIU does
not gain control of the bus until HOLD is removed. This procedure prevents the BIU from just
arbitrarily regaining control of the bus.
Figure 3-36 shows the timing associated with the occurrence of a refresh request while HLDA is
active. Note that HLDA can be as short as one clock in duration. This happens when a refresh
request occurs just after HLDA is granted. A refresh request has higher priority than a bus hold
request; therefore, when the two occur simultaneously, the refresh request occurs before HLDA
becomes active.
Содержание 80C186EA
Страница 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Страница 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Страница 19: ......
Страница 20: ...1 Introduction...
Страница 21: ......
Страница 28: ...2 Overview of the 80C186 Family Architecture...
Страница 29: ......
Страница 79: ......
Страница 80: ...3 Bus Interface Unit...
Страница 81: ......
Страница 129: ......
Страница 130: ...4 Peripheral Control Block...
Страница 131: ......
Страница 139: ......
Страница 140: ...5 ClockGenerationand Power Management...
Страница 141: ......
Страница 165: ......
Страница 166: ...6 Chip Select Unit...
Страница 167: ......
Страница 190: ...7 Refresh Control Unit...
Страница 191: ......
Страница 205: ......
Страница 206: ...8 Interrupt Control Unit...
Страница 207: ......
Страница 239: ...INTERRUPT CONTROL UNIT 8 32...
Страница 240: ...9 Timer Counter Unit...
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Страница 265: ......
Страница 266: ...10 Direct Memory Access Unit...
Страница 267: ......
Страница 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Страница 296: ...11 Math Coprocessing...
Страница 297: ......
Страница 314: ...12 ONCE Mode...
Страница 315: ......
Страница 318: ...A 80C186 Instruction Set Additions and Extensions...
Страница 319: ......
Страница 330: ...B Input Synchronization...
Страница 331: ......
Страница 334: ...C Instruction Set Descriptions...
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Страница 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Страница 384: ...D Instruction Set Opcodes and Clock Cycles...
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Страница 408: ...Index...
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