CLOCK GENERATION AND POWER MANAGEMENT
5-14
If the processor needs to run a refresh cycle during Idle mode, the internal core clock begins to
toggle on the falling CLKOUT edge immediately after the down-counter reaches zero. After one
idle T-state, the processor runs the refresh cycle. As with all other bus cycles, the BIU uses the
ready, wait state generation and chip-select circuitry as necessary for refresh cycles during Idle
mode. There is one idle T-state after T4 before the internal core clock shuts off again.
A HOLD request from an external bus master turns on the core clock as long as HOLD is active
(see Figure 5-11). The core clock restarts one CLKOUT cycle after the bus processor samples
HOLD high. The microprocessor asserts HLDA one cycle after the core clock starts. The core
clock turns off and the processor deasserts HLDA one cycle after the external bus master deas-
serts HOLD.
Figure 5-11. HOLD/HLDA During Idle Mode
As in Active mode, refresh requests will force the BIU to drop HLDA during bus hold. (For more
information on refresh cycles during hold, see “Refresh Operation During a Bus HOLD” on page
3-43 and “Refresh Operation and Bus HOLD” on page 7-12.) Refresh requests will also correctly
break into sequences of back-to-back DMA cycles.
5.2.1.3 Leaving Idle Mode
Any unmasked interrupt or non-maskable interrupt (NMI) will return the processor to Active
mode. Reset also returns the processor to Active mode, but the device loses its prior state.
CLKOUT
Internal
Core Clock
Internal
Peripheral
Clock
HLDA
TI
TI
TI
TI
TI
TI
TI
TI
TI
TI
TI
TI
1 Clock
Delay
Core
Restart
Processor
In Hold
Core Clock
Shuts Off
HOLD
A1120-0A
Содержание 80C186EA
Страница 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Страница 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Страница 19: ......
Страница 20: ...1 Introduction...
Страница 21: ......
Страница 28: ...2 Overview of the 80C186 Family Architecture...
Страница 29: ......
Страница 79: ......
Страница 80: ...3 Bus Interface Unit...
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Страница 130: ...4 Peripheral Control Block...
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Страница 139: ......
Страница 140: ...5 ClockGenerationand Power Management...
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Страница 166: ...6 Chip Select Unit...
Страница 167: ......
Страница 190: ...7 Refresh Control Unit...
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Страница 205: ......
Страница 206: ...8 Interrupt Control Unit...
Страница 207: ......
Страница 239: ...INTERRUPT CONTROL UNIT 8 32...
Страница 240: ...9 Timer Counter Unit...
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Страница 266: ...10 Direct Memory Access Unit...
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Страница 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Страница 296: ...11 Math Coprocessing...
Страница 297: ......
Страница 314: ...12 ONCE Mode...
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Страница 318: ...A 80C186 Instruction Set Additions and Extensions...
Страница 319: ......
Страница 330: ...B Input Synchronization...
Страница 331: ......
Страница 334: ...C Instruction Set Descriptions...
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Страница 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Страница 384: ...D Instruction Set Opcodes and Clock Cycles...
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Страница 408: ...Index...
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