OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2-26
Iteration control instructions can be used to regulate the repetition of software loops. These in-
structions use the CX register as a counter. Like the conditional transfers, the iteration control in-
structions are self-relative and can transfer only to targets that are within –128 to +127 bytes of
themselves. They are SHORT transfers.
The interrupt instructions allow programs and external hardware devices to activate interrupt ser-
vice routines. The effect of a software interrupt is similar to that of a hardware-initiated interrupt.
The processor cannot execute an interrupt acknowledge bus cycle if the interrupt originates in
software or with an NMI (Non-Maskable Interrupt).
Table 2-10. Interpretation of Conditional Transfers
Mnemonic
Condition Tested
“Jump if…”
JA/JNBE
(CF or ZF)=0
above/not below nor equal
JAE/JNB
CF=0
above or equal/not below
JB/JNAE
CF=1
below/not above nor equal
JBE/JNA
(CF or ZF)=1
below or equal/not above
JC
CF=1
carry
JE/JZ
ZF=1
equal/zero
JG/JNLE
((SF xor OF) or ZF)=0
greater/not less nor equal
JGE/JNL
(SF xor OF)=0
greater or equal/not less
JL/JNGE
(SF xor OF)=1
less/not greater nor equal
JLE/JNG
((SF xor OF) or ZF)=1
less or equal/not greater
JNC
CF=0
not carry
JNE/JNZ
ZF=0
not equal/not zero
JNO
OF=0
not overflow
JNP/JPO
PF=0
not parity/parity odd
JNS
SF=0
not sign
JO
OF=1
overflow
JP/JPE
PF=1
parity/parity equal
JS
SF=1
sign
NOTE: The terms above and below refer to the relationship of two unsigned values;
greater and less refer to the relationship of two signed values.
Содержание 80C186EA
Страница 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Страница 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Страница 19: ......
Страница 20: ...1 Introduction...
Страница 21: ......
Страница 28: ...2 Overview of the 80C186 Family Architecture...
Страница 29: ......
Страница 79: ......
Страница 80: ...3 Bus Interface Unit...
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Страница 130: ...4 Peripheral Control Block...
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Страница 139: ......
Страница 140: ...5 ClockGenerationand Power Management...
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Страница 166: ...6 Chip Select Unit...
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Страница 190: ...7 Refresh Control Unit...
Страница 191: ......
Страница 205: ......
Страница 206: ...8 Interrupt Control Unit...
Страница 207: ......
Страница 239: ...INTERRUPT CONTROL UNIT 8 32...
Страница 240: ...9 Timer Counter Unit...
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Страница 265: ......
Страница 266: ...10 Direct Memory Access Unit...
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Страница 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Страница 296: ...11 Math Coprocessing...
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Страница 314: ...12 ONCE Mode...
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Страница 318: ...A 80C186 Instruction Set Additions and Extensions...
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Страница 330: ...B Input Synchronization...
Страница 331: ......
Страница 334: ...C Instruction Set Descriptions...
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Страница 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Страница 384: ...D Instruction Set Opcodes and Clock Cycles...
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Страница 408: ...Index...
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