BUS INTERFACE UNIT
3-6
For word transfers, the word address defines the first byte transferred. The second byte transfer
occurs from the word address plus one. Figure 3-5 illustrates a word transfer on an 8-bit bus in-
terface.
Figure 3-5. 8-Bit Data Bus Word Transfers
3.3 MEMORY AND I/O INTERFACES
The CPU can interface with 8- and 16-bit memory and I/O devices. Memory devices exchange
information with the CPU during memory read, memory write and instruction fetch bus cycles.
I/O (peripheral) devices exchange information with the CPU during memory read, memory write,
I/O read, I/O write and interrupt acknowledge bus cycles. Memory-mapped I/O refers to periph-
eral devices that exchange information during memory cycles. Memory-mapped I/O allows the
full power of the instruction set to be used when communicating with peripheral devices.
I/O read and I/O write bus cycles use a separate I/O address space. Only IN and OUT instructions
can access I/O address space, and information must be transferred between the peripheral device
and the AX register. The first 256 bytes (0–255) of I/O space can be accessed directly by the I/O
instructions. The entire 64 Kbyte I/O address space can be accessed only indirectly, through the
DX register. I/O instructions always force address bits A19:16 to zero.
Interrupt acknowledge, or INTA, bus cycles access an I/O device intended to increase interrupt
input capability. Valid address information is not generated as part of the INTA bus cycle, and
data is transferred only over the lower bank (16-bit device).
A1109-0A
Second Bus Cycle
First Bus Cycle
A19:0
D7:0
D7:0
(X + 1)
(X)
A19:0
Содержание 80C186EA
Страница 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Страница 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Страница 19: ......
Страница 20: ...1 Introduction...
Страница 21: ......
Страница 28: ...2 Overview of the 80C186 Family Architecture...
Страница 29: ......
Страница 79: ......
Страница 80: ...3 Bus Interface Unit...
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Страница 130: ...4 Peripheral Control Block...
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Страница 140: ...5 ClockGenerationand Power Management...
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Страница 166: ...6 Chip Select Unit...
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Страница 190: ...7 Refresh Control Unit...
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Страница 206: ...8 Interrupt Control Unit...
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Страница 239: ...INTERRUPT CONTROL UNIT 8 32...
Страница 240: ...9 Timer Counter Unit...
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Страница 266: ...10 Direct Memory Access Unit...
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Страница 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Страница 296: ...11 Math Coprocessing...
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Страница 314: ...12 ONCE Mode...
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Страница 318: ...A 80C186 Instruction Set Additions and Extensions...
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Страница 330: ...B Input Synchronization...
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Страница 334: ...C Instruction Set Descriptions...
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Страница 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Страница 384: ...D Instruction Set Opcodes and Clock Cycles...
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Страница 408: ...Index...
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