3-47
BUS INTERFACE UNIT
6. Internal error (e.g., divide error, overflow) interrupt vectoring sequence.
7. Hardware (e.g., INT0, DMA) interrupt vectoring sequence.
8. 80C187 Math Coprocessor error interrupt vectoring sequence.
9. DMA bus cycles.
10. General instruction execution. This category includes read/write operations following a
pipelined effective address calculation, vectoring sequences for software interrupts and
numerics code execution. The following points apply to sequences of related execution
cycles.
— The second read/write cycle of an odd-addressed word operation is inseparable from
the first bus cycle.
— The second read/write cycle of an instruction with both load and store accesses (e.g.,
XCHG) can be separated from the first cycle by other bus cycles.
— Successive bus cycles of string instructions (e.g., MOVS) can be separated by other bus
cycles.
— When a locked instruction begins, its associated bus cycles become the highest priority
and cannot be separated (or preempted) until completed.
11. Bus cycles necessary to fill the prefetch queue.
Содержание 80C186EA
Страница 1: ...80C186EA 80C188EA Microprocessor User s Manual...
Страница 2: ...80C186EA 80C188EA Microprocessor User s Manual 1995...
Страница 19: ......
Страница 20: ...1 Introduction...
Страница 21: ......
Страница 28: ...2 Overview of the 80C186 Family Architecture...
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Страница 79: ......
Страница 80: ...3 Bus Interface Unit...
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Страница 130: ...4 Peripheral Control Block...
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Страница 139: ......
Страница 140: ...5 ClockGenerationand Power Management...
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Страница 166: ...6 Chip Select Unit...
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Страница 190: ...7 Refresh Control Unit...
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Страница 205: ......
Страница 206: ...8 Interrupt Control Unit...
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Страница 239: ...INTERRUPT CONTROL UNIT 8 32...
Страница 240: ...9 Timer Counter Unit...
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Страница 266: ...10 Direct Memory Access Unit...
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Страница 295: ...DIRECT MEMORY ACCESS UNIT 10 28...
Страница 296: ...11 Math Coprocessing...
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Страница 314: ...12 ONCE Mode...
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Страница 318: ...A 80C186 Instruction Set Additions and Extensions...
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Страница 330: ...B Input Synchronization...
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Страница 334: ...C Instruction Set Descriptions...
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Страница 383: ...INSTRUCTION SET DESCRIPTIONS C 48...
Страница 384: ...D Instruction Set Opcodes and Clock Cycles...
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Страница 408: ...Index...
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