IDT 89HPES16NT2, Руководство пользователя

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Notes
PES16NT2 User Manual 2 - 1 April 15, 2008
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Chapter 2
Clocking, Reset, and
Initialization
Introduction
The PES16NT2 has two differential reference clock inputs that are used internally to generate all of the
clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both
reference clock input pairs be driven from a common clock source. There are no skew requirements
between the reference clock inputs.The frequency of the reference clock inputs may be selected by the
Reference Clock Mode Select (REFCLKM) input.
Each of the reference clock differential inputs feeds six on-chip PLLs. Each PLL generates a 2.5 GHz
clock which is used by four SerDes lanes and produces a 250 MHz core clock.The 250 MHz core clock
output from one of the six internal PLLs is used as the system clock for internal switch logic.
Each of the reference clock differential inputs feeds six on-chip PLLs. Each PLL generates a 2.5 GHz
clock which is used by four SerDes lanes and produces a 250 MHz core clock. The 250 MHz core clock
output from one of the six internal PLLs is used as the system clock for internal switch logic.
Clock Operation
When the CCLKUS and CCLKDS pins are asserted, they indicate that a common clock is being used
between the upstream device and the upstream port, as well as between the downstream devices and the
downstream port. The Spread Spectrum Clock (SSC) must be disabled when the non-common clock is
used on either the upstream port or downstream port. Figures 2.1 through 2.4 illustrate the operation of the
CCLKUS and CCLKDS clocks using a common clock and a non-common clock.
Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock)
REFCLKM Description
0 100 MHz reference clock input.
1 125 MHz reference clock input.
Table 2.1 Reference Clock Mode Encoding
PES16NT2
Port A
Port C
CCLKDS
CCLKUS
REFCLK0 REFCLK1
EP
Root Complex
Hi
Hi
Clock Generator