IDT 89HPES16NT2, Руководство пользователя

Страница: 134 / 292

IDT Non-Transparent Mode Operation
PES16NT2 User Manual 10 - 4 April 15, 2008
Notes
The mapping tables are initialized using the Mapping Table Address (MTADDR) and Mapping Table
Data (MTDATA) registers in the endpoint configuration spaces. To access a mapping table entry the
Address (ADDR) field in the MTADDR register is initialized with the mapping table entry number. A read
from the MTDATA register returns the current value of the entry while a write modifies the entry.
The MTDATA register must be accessed using Dword operations. Performing a byte or word operation
to the MTDATA register results in no data being modified on a write and zero being returned on a read. In
addition, the MTAERR bit is set in the NTB Status (NTBSTS) register.
Following a reset, all valid (V) bits are cleared. When a valid (V) bit is cleared, the FUNC, DEV, and BUS
fields always return a value of zero when read even if they actually contain a non-zero value (i.e., invalid
entries immediately return a value of zero and are not actually read from the mapping table).
Posted Address Routed Transactions
The internal and external Non-Transparent Bridge (NTB) endpoints contain five Base Address Registers
(BARs) in their Type 0 configuration header. The internal endpoint BARs are PCIE_BAR[0..4] and the
external endpoint BARs are PCEE_BAR[0..4]. BARs zero through three may each be used to map 32-bit
prefetchable or non-prefetchable memory or I/O windows between the internal and external sides of the
non-transparent bridge. Odd and even numbered BARs may be paired to form 64-bit prefetchable address
windows. Thus, the internal and external endpoints may each be configured to support four 32-bit memory
or I/O windows, two 64-bit windows or any combination of the two.
Each BAR has a corresponding setup register, translated base register, and translated limit register in
the Non-Transparent Bridge Configuration Capability structure associated with that side of the non-trans-
parent bridge. For example, PCIE_BAR0 has an associated setup register PCIE_BARSETUP0, translated
base register PCIE_BARTBASE0, and translated limit register PCIE_BARTLIMIT0.
The setup register contains fields that configure the corresponding BAR. For example the type of BAR,
memory or I/O, and the address window size are configured in this register. The base address of a BAR
corresponds to those address bits which are examined to determine if an address falls into a region
mapped by a BAR (i.e., those bits in the Base Address (BADDR) field that can be modified). The remaining
BAR bits form an offset address (i.e., those bits in the Base Address (BADDR) field that cannot be modified
and are read back as zero during configuration).
When an NTB endpoint receives a posted address routed transaction, its address and type are
compared against BARs zero through three. If the type and address match a BAR, the bus, device and
function of the requester ID in the transaction is associatively looked up in the mapping table for that side of
the non-transparent bridge. If a valid entry is found that matches all three fields, the transaction is forwarded
to the other side of the non-transparent bridge if it passes the limit check described below.
The behavior of the device is undefined if an address matches multiple BARs.
Bit
Field Name
Description
0 V When set, this field indicates if the table entry is valid.
18:16 FUNC This field contains the mapping table entry function number.
23:19 DEV This field contains the mapping table entry device number.
31:24 BUS This field contains the mapping table entry bus number.
Table 10.1 Non-Transparent Bridge Mapping Table Fields