IDT 89HPES16NT2, Руководство пользователя

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IDT Clocking, Reset, and Initialization Clock Operation
PES16NT2 User Manual 2 - 3 April 15, 2008
Notes
Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock)
Initialization
A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES16NT2
during a fundamental reset when PERSTN is negated. The boot configuration vector defines essential
parameters for switch operation.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require configuration via an external serial EEPROM. The external serial EEPROM allows
modification of any bit in any software visible register. See Chapter 6, SMBus Interfaces, for more informa-
tion on the serial EEPROM.
The external serial EEPROM and slave SMBus interface may be used to override the function of some
of the signals in the boot configuration vector during a fundamental reset. The signals that may be over-
ridden are noted in Table 2.2. The state of all of the boot configuration signals in Table 2.2 sampled during
the most recent cold reset may be determined by reading the PA_SWSTS register.
Signal
May Be
Overridden
Description
CCLKDS Y Common Clock Downstream. When the CCLKDS pin is
asserted, it indicates that a common clock is being used
between the downstream device and the downstream port. This
pin is used as the initial value of the Slot Clock Configuration bit
in all of the Link Status Registers for downstream ports. The
value may be overridden by modifying the SCLK bit in the
PC_PCIELSTS register.
CCLKUS Y Common Clock Upstream. When the CCLKUS pin is asserted,
it indicates that a common clock is being used between the
upstream device and the upstream port. This pin is used as the
initial value of the Slot Clock Configuration bit in the Link Status
Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.
MSMBSMODE N Master SMBus Slow Mode. The assertion of this pin indicates
that the master SMBus should operate at 100 KHz instead of
400 kHz.
Table 2.2 Boot Configuration Vector Signals (Part 1 of 2)
PES16NT2
Port A
Port C
CCLKDS
CCLKUS
REFCLK0
REFCLK1
EP
Root Complex
Low
Low
Clock Generator
Clock Generator
Clock Generator