IDT 89HPES16NT2, Руководство пользователя

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IDT Transparent Mode Operation
PES16NT2 User Manual 9 - 31 April 15, 2008
Notes
PA_SWCTL - Switch Control (0x0A4)
21 INTB RO 0x0 INTB Aggregated State. Aggregated switch state for
INTB.
0x0 - (negated) INTB negated
0x1 - (asserted) INTB asserted
22 INTC RO 0x0 INTC Aggregated State. Aggregated switch state for
INTC.
0x0 - (negated) INTC negated
0x1 - (asserted) INTC asserted
23 INTD RO 0x0 INTD Aggregated State. Aggregated switch state for
INTD.
0x0 - (negated) INTD negated
0x1 - (asserted) INTD asserted
31:24 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 RST RW 0x0 Reset. Writing a one to this bit initiates a fundamental
reset. Writing a zero has no effect. This field always returns
a value of zero when read.
1 RSTHALT RW HWINIT Reset Halt. When this bit is set, all of the switch logic
except the SMBus interface remains in a reset state. In this
state, registers in the device may be initialized by the slave
SMBus interface. When this bit is cleared, normal opera-
tion ensues.
Setting or clearing this bit has no effect following a reset
operation.
This bit may be set by asserting the RSTHALT signal dur-
ing a reset operation or through initialization by the serial
EEPROM.
2 REGUNLOCK RW 0x0 Register Unlock. When this bit is set, the contents of reg-
isters and fields of type Read and Write when Unlocked
(RWL) are modified when written to. When this bit is
cleared, all registers and fields denoted as RWL become
read-only.
While the initial value of this field is cleared, it is set during
a reset operation, thus allowing serial EEPROM initializa-
tion to modify the contents of RWL fields.
3 DRO RW 0x0 Disable Relaxed Ordering. The switch implements
relaxed ordering for TLPs with the relaxed ordering bit set.
When the DRO bit is set, the switch strongly orders all
transactions regardless of the state of the relaxed ordering
bit in TLPs.
Bit
Field
Field
Name
Type
Default
Value
Description