IDT 89HPES16NT2, Руководство пользователя

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IDT Non-Transparent Mode Operation
PES16NT2 User Manual 10 - 19 April 15, 2008
Notes
Non-Transparent Mode Downstream Port C Configura-
tion Space Organization Registers
All configuration space locations not listed in Table 10.6 return a value of zero when read. Writes to
these locations are ignored and have no side-effects.Port C configuration space registers may be read and
written via the slave SMBus interface and initialized from the serial EEPROM using the CSR system
address formed by adding the base address 0x1000 to the PCI configuration space offset address.
Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
0x000 Word PC_VID PC_VID - Vendor Identification (0x000) on page 10-21
0x002 Word PC_DID PC_DID - Device Identification (0x002) on page 10-21
0x004 Word PC_PCICMD PC_PCICMD - PCI Command (0x004) on page 10-21
0x006 Word PC_PCISTS PC_PCISTS - PCI Status (0x006) on page 10-22
0x008 Byte PC_RID PC_RID - Revision Identification (0x008) on page 10-23
0x009 3 Bytes PC_CCODE PC_CCODE - Class Code (0x009) on page 10-24
0x00C Byte PC_CLS PC_CLS - Cache Line Size (0x00C) on page 10-24
0x00D Byte PC_PLTIMER PC_PLTIMER - Primary Latency Timer (0x00D) on page 10-24
0x00E Byte PC_HDR PC_HDR - Header Type (0x00E) on page 10-24
0x00F Byte PC_BIST PC_BIST - Built-in Self Test (0x00F) on page 10-24
0x010 DWord PC_BAR0 PC_BAR0 - Base Address Register 0 (0x010) on page 10-25
0x014 DWord PC_BAR1 PC_BAR1 - Base Address Register 1 (0x014) on page 10-25
0x018 Byte PC_PBUSN PC_PBUSN - Primary Bus Number (0x018) on page 10-25
0x019 Byte PC_SBUSN PC_SBUSN - Secondary Bus Number (0x019) on page 10-25
0x01A Byte PC_SUBUSN PC_SUBUSN - Subordinate Bus Number (0x01A) on page 10-25
0x01B Byte PC_SLTIMER PC_SLTIMER - Secondary Latency Timer (0x01B) on page 10-25
0x01C Byte PC_IOBASE PC_IOBASE - I/O Base (0x01C) on page 10-26
0x01D Byte PC_IOLIMIT PC_IOLIMIT - I/O Limit (0x01D) on page 10-26
0x01E Word PC_SECSTS PC_SECSTS - Secondary Status (0x01E) on page 10-26
0x020 Word PC_MBASE PC_MBASE - Memory Base (0x020) on page 10-27
0x022 Word PC_MLIMIT PC_MLIMIT - Memory Limit (0x022) on page 10-27
0x024 Word PC_PMBASE PC_PMBASE - Prefetchable Memory Base (0x024) on page 10-28
0x026 Word PC_PMLIMIT PC_PMLIMIT - Prefetchable Memory Limit (0x026) on page 10-28
0x028 DWord PC_PMBASEU PC_PMBASEU - Prefetchable Memory Base Upper (0x028) on page
10-28
0x02C DWord PC_PMLIMITU PC_PMLIMITU - Prefetchable Memory Limit Upper (0x02C) on page
10-29
0x030 Word PC_IOBASEU PC_IOBASEU - I/O Base Upper (0x030) on page 10-29
Table 10.6 Downstream Port C Configuration Space Registers in Non-Transparent Mode (Part 1 of 3)