IDT 89HPES16NT2, Руководство пользователя

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IDT Switch Operation
PES16NT2 User Manual 4 - 5 April 15, 2008
Notes To prevent error flooding, error messages are not sent to the root once the EEPERRC field saturates.
Since PCI Express switches do not normally generate ERR_NONFATAL messages, the Silent End-to-End
Parity Checking bit (SEEPC) bit in the SWSICTL register is provided to disable generation of error
messages and setting of the Detected Parity Error bit when internal corruption is detected.
The default state of the switch following a fundamental reset is to enable this error reporting. (Note that
the Device Control register in the PCI Express capability structure also has a bit that enables generation of
ERR_NONFATAL messages and that the default value of this bit is to disable these messages.)
In addition to TLPs that flow through the switch, cases exist in which TLPs are produced and consumed
by the switch (e.g., a configuration requests and responses). Whenever a TLP is produced by the switch,
parity is computed as the TLP is generated. Thus, error protection is provided on produced TLPs as they
flow through the switch. In addition, parity is checked on all consumed TLPs. If an error is detected, the TLP
is discarded and an error is reported using the mechanism described above.
This means that a parity error reported at a switch port cannot be definitively used to identify the location
at which the error occurred as the error may have occurred when parity as generated at another port, in the
switch core, or may have been generated locally (i.e., for ingress TLPs to the switch core which are
consumed by the port such as Type 0 configuration read requests on the root port).
Switch Time-Outs
The switch discards any TLP that reaches the head of an input buffer and is more than 50ms old. For
non-posted and completion TLPs, the requester’s completion time-out mechanism will detect discarded
TLPs. No similar mechanism exists in PCIe for posted TLPs. Therefore, whenever a posted TLP is
discarded by the switch due to a time-out, an error non-fatal (ERR_NONFATAL) message (if this message
reporting is enabled) is sent to the root.
Whenever a TLP is discarded from a posted input buffer, the Posted TLP Time-out Count (PTLPTOC)
field is incremented in the Switch System Integrity Time-Out Drop Count (SWSITDCNT) register in the port
on which the TLP was received. This is a saturating counter that is automatically cleared when read. When-
ever a TLP is discarded from a non-posted input buffer, the Non-Posted TLP Time-out Count (NPTLPTOC)
field is incremented in this register and whenever a TLP is discarded from a completion input buffer, the
Completion TLP Time-out Count (NPTLPTOC) field is incremented.
To prevent error flooding, error messages are not sent to the root once the PTLPTOC counter saturates.
Since PCI Express switches do not normally generate ERR_NONFATAL messages, the Silent Posted TLP
Time-out (SPTLPTO) bit in the SWSICTL register is provided to disable generation of error non-fatal
messages. When this bit is set, ERR_NONFATAL messages are not generated when posted transactions
received on the corresponding port are discarded. The PTLPTOC field however is always updated.
Interrupts
The PES16NT2 supports legacy PCI INTx emulation where x is A, B, C or D. Rather than use sideband
INTx signals, PCIe defines two messages that indicate the assertion and negation of an interrupt signal. An
Assert_INTx message is used to signal the assertion of an interrupt signal and an Deassert_INTx message
is used to signal its negation.
The PES16NT2 maintains an aggregated INTx state for each of the four interrupt signals (i.e., A through
D). The value of the INTA, INTB, INTC, and INTD aggregated state may be determined by examining the
corresponding fields in the PA_SWSTS register. The aggregated INTx state of each port for each of the four
interrupt signals (i.e., A through D) on the primary side of its PCI to PCI bridge may be determined by exam-
ining the state of the INTA, INTB, INTC, and INTD fields in the corresponding port’s Interrupt Status
(PA_INTSTS and PC_INTSTS) register.
An Assert_INTx message is sent to the root by the upstream port (i.e., port A), when the aggregated
state of the corresponding interrupt in the switch transitions from a negated to an asserted state. A
Deassert_INTx message is sent to the root by the upstream port when the aggregated state of the corre-
sponding interrupt transitions from an asserted to a negated state.