IDT 89HPES16NT2, Руководство пользователя

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IDT PES16NT2 Device Overview
PES16NT2 User Manual 1 - 7 April 15, 2008
Notes
Pin Description
The following tables list the functions of the pins provided on the PES16NT2. Some of the functions
listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals
ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals
(including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic
one (high) level.
Signal Type Name/Description
PEALREV I PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PEARP[7:0]
PEARN[7:0] I PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PEATP[7:0]
PEATN[7:0] O PCI Express Port A Serial Data Transmit. Differential PCI Express trans-
mit pairs for port A
PECLREV I PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PECRP[7:0]
PECRN[7:0] I PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PECTP[7:0]
PECTN[7:0] O PCI Express Port C Serial Data Transmit. Differential PCI Express trans-
mit pairs for port C
PEREFCLKP[1:0]
PEREFCLKN[1:0] I PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM I PCI Express Reference Clock Mode Select. These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1.3 PCI Express Interface Pins
Signal Type Name/Description
MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM is being accessed.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 1.4 SMBus Interface Pins