Table 55 Memory Subsystem Events That May Light Diagnostic Panel LEDs (continued)
Notes
Source
Cause
Sample IPMI Events
Diagnostic
LEDs
SFW
System firmware
(SFW) was unable to
Type E0h, 187d:26d
MEM_ECC_MBE_SIGNAL_TST_FAILED
Processor
Carrier
clear the platform
error logs on the CEC
SFW
The error registers in
the CEC failed to
clear
Type E0h, 190d:26d
MEM_ERR_REG_CLEAR_FAILURE
Processor
Carrier
SFW
The CEC’s memory
controller failed the
register test
Type E0h, 208d:26d MEM_MC_REG_FAILURE
Processor
Carrier
Voltage wholly
contained on
BMC
Expander voltage
error
Type 02h, 02h:07h:06h
VOLTAGE_NON_RECOVERABLE
Memory
Carriers
memory
expander
shows failure
The failing
DIMM’s rank
SFW
Detected that an
SDRAM is failing on
the DIMM
Type E0h, 4000d:26d
MEM_CHIPSPARE_DEALLOC_RANK
DIMMs
will be
deallocated
SFW
DIMM type is not
compatible with
Type E0h, 174d:26d
MEM_DIMM_TYPE_INCOMPATIBLE
DIMMs
current DIMMs for this
platform
SFW
Detected a fatal error
in DIMM’s serial
Type E0h, 173d:26d MEM_DIMM_SPD_FATAL
DIMMs
presence detect
(SPD)
24 / 48 slot
version of
SFW
DIMM mismatch
found within rank of
four
Type E0h, 795d:26d
MEM_DIMM_QUAD_MISMATCH
DIMMs
memory
carrier
8 slot version
of memory
carrier
SFW
DIMM mismatch
found within rank of
two
Type E0h, 779d:26d
MEM_DIMM_PAIR_MISMATCH
DIMMs
Troubleshooting SBA
The server shares a common I/O backplane that supports a total of 10 PCI slots: slots 1-2 on
systems with only one core I/O SAS card, and slots 1, 2, and 10 for systems with two core I/O
SAS cards, are for customer use. Slots 2-10 are used for core I/O functions on systems with only
1 SAS core I/O card; slots 2-9 are used on systems with 2 SAS core I/O cards. The System Bus
Adapter (SBA) logic within the zx2 chip of a server uses 16 rope interfaces to support up to eight
Lower Bus Adapter (LBA) chips. Each LBA chip interfaces with the SBA in the zx2 chip through
one or multiple rope interfaces, as follows:
•
One LBA chip uses a single rope interface (used by core I/O) to support a single 32-bit PCI
slot running at 33 MHz;
•
Three LBA chips use a single-rope interface (one used by core I/O and two are for customer
use) to support dual 64-bit PCI-X slots running at 66 MHz;
160
Troubleshooting