Model 3585A
Circuit Functional Descriptions
6·26. DISPLAY DESCRIPTION (Service Group D)
The Display Section Block Diagram gives a very good idea of of how the Display Section
works. As each board of the Display is discussed, refer to Figure 6-14. Display Block
Diagram in this manual section and the schematic drawings found in Service Group D of
Volume Two.
The A61 , Clock Generator, board takes a 10 MHz reference from the A21 Reference board,
limits it, squares it up and sends it on to the A46 Counter board. The A61 board takes the
same 10 MHz signal and divides it by ten to get a 1 MHz reference signal. This 1 MHz signal
then follows two separate paths. One is a -;- 1 2 PLL that produces a 12 MHz signal for the
central processor. The other is a -;- 8 PLL that produces an 8 MHz signal for the A63 Display
Processor board. The 8 MHz signal is also -;- 2 to get a 4 MHz signal for the A44 HP-IB
board.
The A63 , Digital Display Driver, board has many functions. An Active Clock Pull-up circuit
creates a fast rise time, 4 MHz master clock. Input Latches are used to latch the DMA infor
mation onto the board. A display processor along with its own ROM and instruction set
controls the display operation. A timer refreshes the display once every 1 7 msec. The
alphanumeric generator along with the alphanumeric ROM generate all alphanumeric
characters. An octal latch for y-axis alphanumerics and a 10 bit multiplexer/latch are used to
latch the y-axis and x-axis alphanumerics, respectively. The 10 bit multiplexer also latches
the y-axis graphics . U36 and U47 determine the vertical length of the line to be drawn and,
subsequently, supply the appropriate control logic to the programmable amplifier on the
A64 board is controlled by the line length controller. This board also generates external plot
ter controls, control signals for sampling, sweeping, and ramping.
The A64 board is the Analog Display Driver. This board takes the digital data from the A63
board and converts it into analog signals usable by the display. Consider the graphics first. A
lO-bit DAC receives the y-axis data from the A63 board and converts the incoming data to
an analog current. This current is then converted into a voltage. The voltage is then
amplified by a programmable amplifier. A programmable amplifier is used so that longer
lines appearing on the display appear with the same intensity as shorter lines. To explain fur
ther, if all lengths of lines were drawn in the same amount of time, the long lines would not
be as bright as the short ones; therefore, the programmable amplifier in conjunction with
the variable drawing time create comparably bright lines of the correct length.
The output of the programmable amplifier is buffered and then goes to a sample and hold
circuit. A follower/buffer then transfers the voltage to an integrator that controls the ver
tical line drawn on the display.
The x-axis graphics is a ramp that causes a sweep from left to right. (L)RAMP ENABLE
signals the ramp current source to cause the ramp generator integrator to charge, thereby
causing a sweep. (H)SWP signals the retrace from right to left to prepare for the next ramp.
This signal causes the sweep integrator capacitor to discharge. The ramp remains on for 5
usec for each y-axis sample. For lines that take longer than 5 usec to draw, the ramp turns on
for 5 usec then off for the remaining time necessary to draw that particular vertical line.
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