Model 3585A
Circuit Functional Descriptions
To understand the pulse removal portion of Fractional N, the -;- N block must first be fully
understood. To divide the YCO frequency by an integer number (N
=
400 for example), the
YCO will set to 40 MHz. An output of 100 kHz from the -;- N block is desired. When N is
chosen as 400, a counter is set to count to 400. The counter's input is the YCO frequency. Its
output will be a pulse which occurs once for each 400 input pulses. The frequency has then
been divided by that integer.
If fractional N is desired, the counter which effectively divides the YCO frequency will have
a changing value. For example, let the output frequency be 40.04 MHz. To get a phase
detector input of 100 kHz, the effective N is 40.04 MHz divide by 100 kHz or 400.4. To ac
complish dividing by 400.4, the counter is first set to -;- 400 for 60"70 of the time and it will
-;- 401 for 40"70 of the time. The -;- 401 is referred to as pulse removal since the counter has to
receive one more YCO cycle before it outputs a pulse.
The pulse removal command is controlled by the phase accumulation register. This register
contains the total fractional part which has been accumulated at any given time. An example
will show how the frational part of N is added to the register and the overflow is used to con
trol the pulse remove command.
Example:
Let the output frequency equal 40.04 MHz and the phase detector input is 100
kHz; therefore, the -;- N fractional must be 40.04 MHz divided by 100 kHz or
400.4.
Ph,ase Accumulation Register:
.0000
+
.4000
.4000
+
.4000
.8000
+
.4000
1 .2000
+
.4000
.6000
+
.4000
1 .0000
+
.4000
.4000
initially set to zero
first cycle (10 usec)
second cycle (20 usec)
third cycle (30 usec) a pulse remove is initiated because of the carry
digit
fourth cycle (40 usec) no pulse remove because no carry was initiated
fifth cycle - pulse remove is generated because of the carry
cycles repeat
To get an overall idea of how Fractional N is implemented in the -hp- 3585A, look at the
Fractional N Loop portion of Figure 6-12. Local Oscillator Block Diagram. Circuit boards
will be discussed in the order appearing in the block diagram: A33, A32 and A3 1 . (Refering
to the applicable board schematic may be helpful in understanding circuit operation.)
The A33, Divide By N Counter, board contains the Fractional N Control chip through
which the API's and counters are programmed. This chip and its associated circuitry also
generate many clocks and control logic signals. For the most part, the remaining circuitry on
the board is a programmable
-;-
N counter. U4 and U5 are a -;- 2 (or -;- 3 during pulse
swallow), U 1 2 and U l 3 are a -;- N where N
=
1 to 5, and U14 and U 1 5 are both program
mable -;- 10. Together they form a -;- N circuit where N
=
250 to 600. This divided-down
Scans by ARTEK MEDIA =>
6-23
