Model 3585A
Circuit Functional Descriptions
O U T P U T
V C O
4 0 M H z
3 0- 5 0M H z
r40MHz)
+ �
DC C O RR E C T I ON V O L TA G E
1 1 0 0KHz)
R E F E R E N C E
P H A S E
1 0 0KHz
COMPARATOR
35851\-6-9
Figure 6-9. Standard Phase Lock Loop
The frequency of the VCO is controlled by the dc correction voltage out of the phase detec
tor. In this example, the phase detector "sees" no difference in the phase of the inputs, thus
the dc correction voltage has no effect on the VCO frequency. To change the frequency, the
N need only be changed. If it were set to 500, the phase detector input would change to 80
kHz. Compared to the 1 00 kHz reference frequency, this shows a constantly changing
phase. The dc correction voltage output of the phase detector will change, which will vary
the VCO frequency in the proper direction. It will "lock in" at a frequency of 50 kHz which
divided by 500 leaves 100 kHz at the phase detector input.
Figure 6-10 shows a PLL with a sample and hold circuit added. The circuit operation is as
follows:
1 . The phase detector/comparator output is a current source which charges up the in
tegrator's capacitor for a specific amount of time
2. The sample/hold switch transfers the integrator voltage to the sample/hold circuit.
3 . This voltage is stored on the sample/hold capacitor and it is amplified and used for the
dc correction voltage.
4. The bias current source is then turned on to discharge the integrator because the
voltage would continue to build up.
5. The cycle then repeats itself.
Suppose we desire a frequency which requires a
-+
N more than three digits. An output fre
quency of 40.04 MHz would require a divide by N of 400.4. This is referred to as divide by N
fractional. The existing circuit would not allow the fractional part. The pulse remove com
mand and Analog Phase Interpolator (API) control are required to accomplish the desired
divide by N fractional. See Figure 6- 1 1 . Fractional N Phase Lock Loop.
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6-21
