Sc:ans
by => AR7EK JIIED�
@ 2003-2005
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ANAL OG T O
11/ 0
DI SPLAY
HAND SHAKE
INPUTS
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TO COUN T ER
1 s t - G )
AND HP- IB ( SG-F)
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01
I�������T
LDMARC LDMAIR
CONlITROOL
LATCH
LI OD3
LFLG
DECODER
UIB . 1 9
I
LATCH
U1 1 . 1 2
TRACKING
GEN ERATOR AND
INPUT SECT I ON
DATA
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CONTROL LINE
PROCESSING
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LATCH
AND CONTROL
U
3
. 4
B
J
RP
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I
LATCH
U 1 5 . 16
PROCESSOR
DATA
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1
1 00 BUS
1/0 STATUS BUS
CENTRAL PROCESSOR
U13
I/O
STATUS
BUFFER
RESET
RESET
CIRCUI TRY
LDCLR
rop 01 02
l
DUAL
12MHz
CLO CK
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SELF TEST
CI RCUIT
U 1 8 . 16 . 1 2
l OA BUS
IIEHORY CONTROL BUS
"" FOR
MEMORY CON
MH OUTPUT
lRI- STATE
CONTROL
l OA BUS
L OW
LAT CH
U33 . 34
ORDER
LAT CH
t SOB
U33 . 34
MUL TI-
C�N
.
LSTII
MEMORY
4K
X 1 6
DYNAM I C RAM
I
tMES
U36
HEMORY ENABLE
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CONTROL
REFRESH
ADDRES S
COUNTER
U 1 9 . 27
UB
REFRESH
CONTROL
U9
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- 1
,
TP3
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16 LINES
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LRBFO
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3 TO
B
D ECODER
I
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Figure 6- 1 3 . Processor, I/O and Keyboard Block Diagram
6-29/6-30