590
A.2.26
DMA Transfer Count Registers 0–3 (TCR0–TCR3)
DMAC
•
Start Address: H'5FFFF4A (channel 0), H'5FFFF5A (channel 1), H'5FFFF6A (channel 2),
H'5FFFF7A (channel 3)
•
Bus Width: 16/32
Register Overview:
Bit:
15
14
1312
11
10
9
8
Bit name:
Initial value:
*
*
*
*
*
*
*
*
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
32
1
0
Bit name:
Initial value:
*
*
*
*
*
*
*
*
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Undetermined
Table A.27 TCR0–TCR3 Bit Functions
Bit
Bit name
Description
15–0
(Specifies number of DMA
transfers)
Specifies the number of DMA transfers (bytes or
words). During DMA transfer, indicates the number of
transfers remaining.
Содержание HD6417032
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Страница 525: ...490 CK RAS CAS TRp TRc TRcc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 18 Self Refresh ...
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