167
8.10.1
Operation of Bus Arbitration
If there is conflict between bus arbitration and refreshing, the operation is as follows.
1. If DRAM refreshing is requested in this chip when the bus is released and
BACK
is low,
BACK
goes high and the occurrence of the refresh request can be indicated externally. At this
time, the external device may generate a bus cycle when
BREQ
is low even if
BACK
is high.
Therefore, the bus remains released to the external device. Then, when
BREQ
goes high, this
chip acquires bus ownership, and executes a refresh and the bus cycle of the CPU or DMAC.
After the external device acquires bus ownership and
BACK
is low, a refresh is requested
when
BACK
goes high even if
BREQ
input is low. Therefore, drive
BREQ
high immediately
to release the bus for this chip to hold DRAM data (see figure 8.36).
2. When
BREQ
changes from high to low and an internal refresh is requested at the timing of bus
release by this chip,
BACK
may remain high. The bus is released to the external device since
BREQ
input is low. This operation is based on the above specification (1). To hold DRAM
data, drive
BREQ
high and release the bus to this chip immediately when the external device
detects that
BACK
does not change to low during a fixed time (see figure 8.37). When a
refresh request is generated and
BACK
returns to high, as shown in figure 8.37, a momentary
narrow pulse-shaped spike may be output where
BACK
was originally supposed to go low.
BACK
BREQ
Refresh demand
Refresh execution
Figure 8.36
BACK
Operation in Response to Refresh Demand (1)
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Страница 525: ...490 CK RAS CAS TRp TRc TRcc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 18 Self Refresh ...
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