531
Table 20.20 Bus Timing (2) (cont)
Conditions: V
CC
= 3.3 V ±0.3V, AV
CC
= 3.3 V ±0.3V, AV
CC
= V
CC
±0.3V, AV
ref
= 3.0 V to
AV
CC
, V
SS
= AV
SS
= 0 V,
φ
= 12.5 MHz, Ta = –20 to +75°C*
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item
Symbol
Min
Max
Unit
Figures
Write data delay time 1
t
WDD1
—
70
ns
20.53, 20.57, 20.58,
20.63
Write data delay time 2
t
WDD2
—
40
ns
20.55, 20.56
Write data hold time
t
WDH
–10
—
ns
20.53, 20.55–20.58, 20.63
Parity output delay time 1
t
WPDD1
—
80
ns
20.53, 20.57, 20.58
Parity output delay time 2
t
WPDD2
—
40
ns
20.55, 20.56
Parity output hold time
t
WPDH
–10
—
ns
20.53, 20.55–20.58
Wait setup time
t
WTS
40
—
ns
20.54, 20.59, 20.63
Wait hold time
t
WTH
10
—
ns
Read data access time 1
*
4
t
ACC1
t
cyc
– 44
—
ns
20.52, 20.55, 20.56
Read data access time 2
*
4
t
ACC2
t
cyc
×
(n+2) –
44
*
2
—
ns
20.53, 20.54, 20.57–20.59
RAS
delay time 1
t
RASD1
—
40
ns
20.55–20.58,
RAS
delay time 2
t
RASD2
—
40
ns
20.60–20.62
CAS
delay time 1
t
CASD1
—
40
ns
20.55
CAS
delay time 2
*
5
t
CASD2
—
40
ns
20.57, 20.58,
CAS
delay time 3
*
5
t
CASD3
—
40
ns
20.60–20.62
Column address setup time
t
ASC
0
—
ns
20.55, 20.56
Read data access
time from
CAS
1
*
4
35% duty
*
1
t
CAC1
t
cyc
×
0.65 –
35
—
ns
50% duty
t
cyc
×
0.5 – 35 —
ns
Read data access time from
CAS
2
*
4
t
CAC2
t
cyc
×
(n+1) –
35
*
2
—
ns
20.57–20.59
Read data access time from
RAS
1
*
4
t
RAC1
t
cyc
×
1.5 – 35 —
ns
20.55, 20.56
Read data access time from
RAS
2
*
4
t
RAC2
t
cyc
×
(n+2.5)
– 35
*
2
—
ns
20.57–20.59
High-speed page mode
CAS
precharge time
t
CP
t
cyc
×
0.25
—
ns
20.56
Содержание HD6417032
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Страница 525: ...490 CK RAS CAS TRp TRc TRcc tRASD1 tRASD2 tCASD3 tCASD2 TRr tCSR Figure 20 18 Self Refresh ...
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